July 16, 2012 -- Aldec, Inc. has announced a webinar on July 19 that will address the challenging task faced by engineers in implementing constrained random stimulus or functional coverage in their testbenchs. VHDL designers used to make difficult choices between "reinventing the wheel" (writing appropriate code from scratch) and !using a square wheel! (using SystemVerilog for verification).
This webinar will demonstrate a third option; the Open Source VHDL Verification Methodology OS-VVM, a set of VHDL packages that provide reliable, field-tested procedures and functions handling randomization and functional coverage. Attendees will learn about the structure and use of OS-VVM packages, paying special attention to Smart Coverage that combines random stimulus and functional coverage to provide faster verification.