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The Evolution of Power Format Standards  
Contributor: Cadence Design Systems, Inc.
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July 16, 2012 -- The Silicon Integration Initiative's (Si2's) contribution of the Open Low-Power Methodology (OpenLPM) to the IEEE in 2011 marked an important milestone in the development of power-format standards for the industry. Cadence, among many other industry leaders, supports this contribution because it shows the most promising path for the industry to converge on one power-format standard. Methodology convergence, however, is a pre-requisite for future power-format convergence.

Cadence led the industry with the formation of the Power Forward Initiative and the introduction of a complete RTL-to-GDSII low-power solution enabled by the Si2's Common Power Format (CPF) more than six years ago. At that time, the industry was not quite sure whether the power-intent side-file approach was the right methodology to address the challenges of advanced low-power design. At present, the Cadence Low-Power Solution has achieved wide adoption and has been proven by hundreds of design tape-outs around the world.

This article explains what methodology convergence is; why the OpenLPM is a promising step toward power format convergence; and how Cadence technologies can help engineers develop low-power designs successfully while the industry is progressing along the path to convergence.

Fundamental differences between UPF and CPF

IEEE 1801-2009, which includes the Accellera Unified Power Format (UPF) 1.0, is an alternative power format. Although UPF 1.0 shares similarities with CPF, it has some fundamental differences in how the power intent is defined. In CPF, power intent is primarily described by an abstract data object called a "power domain" starting at the register transfer level (RTL).

As the design flow evolves from RTL design to physical design, each power domain will eventually be refined into a primary set of power supplies to uniquely define this power domain. UPF 1.0, however, lacks such abstraction capability, so an RTL designer using UPF 1.0 has to describe the exact physical power network at RTL. The main difficulty with this approach is that RTL designers do not have the complete physical power network information.

There are other major differences between UPF 1.0 and CPF, such as how the isolation and level-shifter logic between power domains is defined. IEEE 1801-2009 introduces the concept of the supply set, which has many similar properties to the power domain in CPF, and many other constructs to close the methodology differences between UPF 1.0 and CPF (such as the way to specify isolation and level-shifter logic using the driving/ receiving power domain of a signal).

 

Figure 1. A simple design with power gating.

 

An example of a simple design with two power domains. The design has one external supply VDD and one of the internal blocks uses the switched version of the top supply, controlled by the signal pon at the top level.

To describe the above design using UPF 1.0, the power-intent file would be as follows:

 

Figure 2. Power intent in UPF 1.0.

 

As indicated by Figure 2, designers using UPF 1.0 have to lay out almost the complete physical power structure at RTL, which is not only a difficult task, but also a completely unnecessary one. Using the power domain concept in CPF or the supply set construct in IEEE 1801, the power intent of the example design can be described easily at RTL, as shown in Figure 3. (Note that in this example the implicit supply set of power domain PD_green is used, referred to as "PD_green.primary.")

 

Figure 3a. Power intent in IEEE 1801

 

Figure 3b. Power intent in CPF.

 

It is clear that the methodology to describe power intent at RTL by using either CPF or the new constructs in IEEE 1801 is a much better approach than that of UPF 1.0. Unfortunately, the IEEE 1801 standard has included all the constructs from UPF 1.0. As a result, there are two radically different methodologies within the same standard to describe the same power intent. Such a mix of methodologies in the same standard not only creates confusion for users but also adds unnecessary difficulties for tool vendors to support the standard. It is no surprise that three years after the release of IEEE 1801-2009, we just started to see limited support by EDA tools for the new 1801 methodology of power intent specification. Many EDA tool vendors who already support UPF 1.0 have chosen merely to continue with the Accellera UPF 1.0 approach for their support of the IEEE 1801 format.

This explains why designers who want to use IEEE 1801-2009 are pressuring vendors to support the true essence of the 1801-2009 specification, not just the UPF 1.0 method that was included in the initial 1801-2009 specification for Accellera compatibility. There are strong signs both within the EDA industry and the user community that the momentum is finally shifting to facilitate this change.

Figure 4 illustrates the current status of all power standards:

 

Figure 4. Current status of all power formats.

 

Power format convergence requires methodology convergence

To achieve full interoperability among different vendors supporting different power formats, the methodology differences between CPF and IEEE 1801 must be addressed. Cadence supports the effort to develop a converged power methodology with the IEEE 1801 Working Group. There are two major objectives to be achieved through this effort. First, IEEE 1801 needs to define a process to censure the incompatible methodology as enabled by some UPF 1.0 constructs (such as power supply net-driven power intent specification). Second, the Si2 needs to contribute the Open Low-Power Methodology, or OpenLPM, which consists of a set of unique CPF features that are currently not available in IEEE 1801. One such feature is the formal hierarchical design approach, including macro modeling for hardened intellectual property (IP).

To facilitate this methodology-convergence effort, Cadence joined the IEEE 1801 Working Group as a voting corporate member in 2011. Since then, significant progress has been made at the standard organizations, where Si2 contributed the OpenLPM to IEEE around DAC 2011 and the IEEE 1801 Working Group is currently working on a new release which will reduce the impact of the old UPF 1.0 methodology on the standard. Such an effort will benefit all EDA suppliers, as it eliminates redundant investment in multiple and conflicting methodologies and formats.

The Cadence Low-Power Solution

The Cadence Low-Power Solution currently enables mixed-tool-flow interoperability through support for UPF using an import feature in the Encounter Conformal Low Power product. Conformal Low Power can import a UPF file along with the corresponding design and library, and export a semantically equivalent CPF file. The CPF file can then be used by other Cadence tools to continue the design flow. Until the converged methodology becomes a reality, Cadence will continue to provide format interoperability using Conformal Low Power import support for IEEE 1801-2009.

The CPF-enabled Cadence Low-Power Solution has been leading the industry with its comprehensive and mature technology (see Figure 5). The classical technologies included in the solution are Incisive Enterprise Simulator (for low-power functional verification), Virtuoso AMS Designer (for power domain-aware mixed-signal simulation), Encounter RTL Compiler (for power-aware logic synthesis and design-for-test synthesis), Encounter Conformal Low Power (for power-aware formal verification), Encounter Test (for power-aware automatic test pattern generation), Encounter Digital Implementation System (for power-aware physical implementation), Encounter Power System (for power integrity sign-off analysis), and Encounter Timing System (for timing sign-off).

 

Figure 5. Overview of Cadence technologies enabled by CPF.

 

Most recently, Cadence added Virtuoso and Palladium technologies into the CPF-enabled solution suite. Automatic CPF import/ export in the Virtuoso environment enables static verification of the power structures of a schematic using Conformal Low Power. CPF-enabled emulation and hardware acceleration in the Palladium system is the only solution that addresses system-level verification of power management using real system software or applications.

 

By Qi Wang, Ph.D.

Qi Wang is currently the Group Director for the Solutions Marketing at Cadence with a focus on low power and mixed-signal solutions. He was the leading architect to drive the development of the end-to-end Cadence Low Power Solution and was the chief architect of Common Power Format, which was contributed to Si2 and became the industry first open power format in early 2007. As the Vice Chair of the Low Power Coalition and the Chair of the Format Working Group at Si2.org, he is also actively driving the industry coalition to promote advanced low power designs and methodologies. Prior to joining Cadence in 1998, he held various R&D positions in the area of low power synthesis.

Resources

Power Forward Initiative

A Practical Guide for Low-Power Design

Open Low-Power Methodology Ushers in New Era of Low-Power Interoperability

Power Intent Formats: Light at the End of the Tunnel?

 


Go to the Cadence Design Systems, Inc. website to learn more.

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, power analysis, power optimization, low power design, low-power design, Unified Power Format, UPF, Common Power Format, CPF, SOCcentral, Cadence Design Systems,
488/38846 7/16/2012 4363 4363
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