July 18, 2012 -- Cadence Design Systems, Inc. announced today that Renesas Electronics Corp. significantly improved power, area and productivity by using Cadence Encounter digital technology to tape out its new generation of automotive 32-bit microcontrollers (MCU). These latest MCUs were designed specifically for integrating system-control and network-processing functions of car infotainment devices on one chip.

In modern MCU designs, clock networks can contribute about a third of overall chip power consumption. Using key technology from the Encounter RTL-to-GDSII flow, Renesas reduced clock power by 30% on its new MCUs. Furthermore, the Cadence Encounter Digital Implementation (EDI) System and its new Clock Concurrent Optimization (CCOpt) technology enabled Renesas to automate complex timing closure using clock-delay control to and from hard macros simultaneously with datapath optimization. As a result, Renesas engineers were able to successfully deliver an MCU solution that supports multiple high-bandwidth protocols such as Ethernet and MOST (Media Oriented System Transport).

"The EDI System enabled our engineers to eliminate several manual steps and tape out a 160-MHz device with reduced power and area, while hitting our performance target and market window," said Hiroyuki Suzuki, Associate General Manager of the MCU Product-Design Division of Renesas Electronics.

The integrated Cadence flow includes Encounter RTL Compiler, sign-off-proven Cadence and Encounter Timing System. In addition, the CCOpt technology unifies clock-tree synthesis with logic/ physical optimization resulting in significant power, performance and area improvements.

Posted by: John Miklosz