July 18, 2012 -- Synopsys, Inc. today announced the availability of the 2012.06 release of its IC Compiler software, featuring multiple advances to support giga-performance design. This latest release of IC Compiler focuses on helping IC designers achieve higher clock frequencies more efficiently. New capabilities include optimizations that can boost operating clock speeds, expanded support for highly fragmented floorplans and new technologies that address advanced process effects.

"Renesas Electronics is a premier provider of advanced semiconductor solutions," said Tatsuji Kagatani, Department Manager, Back-End Design Technology Development Department at Renesas Electronics Corp. "We rely on continuous technology innovation in IC Compiler to realize our very challenging designs with clock-speed targets of well over 1GHz and/or lower power consumption with aggressive time-to-market goals. In our recent study of IC Compiler's new multi-source CTS technology on a design with several complex clocks, we were easily able to meet our demanding skew and latency targets."

The IC Compiler 2012.06 release contains several new technologies geared towards boosting design frequency. Clock distribution using a mesh structure has been a staple of high-performance designs to minimize variation. However, mesh flows are complex and require expert user knowledge to manage power efficiently. Multi-source clock-tree synthesis (CTS) is a new technology that leverages automated clock-tree and mesh techniques to provide better variation tolerance than traditional CTS, while consuming less power than a mesh.

Processor designers favor the performance scalability and smaller device geometries offered at lower process nodes. In this release, new algorithms leverage advanced process effects to improve timing, reduce buffer count and create more robust circuits for reduced variability. In addition, IP-dominated designs often have highly fragmented floorplans characterized by narrow channels between blocks and a large number of macros and pipelined registers. The latest IC Compiler release can improve timing and routability for such designs. The 2012.06 release also delivers several enhancements which enable designers to achieve target frequency. Transparent interface-optimization technology has been improved to provide better timing and faster time to results. In-Design physical verification enables power-network verification and improved run-time for foundry-required metal-fill insertion.

Posted by: John Miklosz