July 30, 2012 -- Power noise integrity (PNI) is becoming a number one IC design focus, as product quality, circuit reliability and lifetime robustness are increasingly important parameters of strategic business value in high-volume IC products. All the while, higher levels of SOC integration, advanced low-power design techniques, increasing power density and faster circuit switching at scaling process nodes are causing critical PNI challenges at 28nm and beyond. Power delivery network (PDN) design is an increasingly complicated task, and key to semiconductor business success.
By Tobias Bjerregaard. (Bjerregaard is CEO and founder of Teklatech.)
This brief introduction has been excerpted from the original copyrighted article.
Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, signal integrity, noise, power analysis, power optimization, EE Times EDA Designline, Teklatech
