September 10, 2012 -- Mentor Graphics Corp. today announced availability of an update to the Universal Verification Methodology Connect (UVM Connect) to bring the benefits of it to the Open Verification Methodology (OVM) community. UVM Connect has been extended to allow it to be compiled to run with the OVM. The UVM Connect architecture facilitates easy connection with other environments beyond the initially supported UVM and SystemC. With UVM Connect 2.2, teams using OVM can connect with SystemC models and other environments as well.

Market research shows OVM continues to be a popular and growing methodology for verification teams. About half of all teams have adopted OVM as their verification base-class library and it continues to lead among all other alternatives. To support the OVM community, the Mentor Graphics Verification Academy offers a user community forum and contributions area that encourages users to share their OVM experiences and enhancements with each other. The Verification Academy also has educational and training information to help the novice to the expert.

"When looking at functional verification trends, it was clear that OVM remains important to the verification community and its growth is projected to continue," said Harry Foster, Chief Verification Scientist of the Design Verification Technology division at Mentor. "Mentor continues to demonstrate its support of OVM by making significant new UVM capabilities available to the OVM community and promoting a vibrant OVM community at the Verification Academy."

The enhanced UVM Connect provides standard TLM connectivity between models written in SystemC and OVM SystemVerilog to maximize IP reuse. It is designed to work with all simulators that support the IEEE 1800 SystemVerilog and IEEE 1666 SystemC standards and can accommodate different inter-language instantiation schemes used in various solutions. Feedback from verification teams with simulators from multiple suppliers was taken into account to provide broad industry support.

About UVM Connect

Design and verification teams work with a number of functional models sourced in different design languages, primarily SystemC and SystemVerilog, where the choice of language is made in order to exploit the advantages of the native language. By facilitating cross-language communication via standard transaction-level modeling (TLM) interfaces, UVM Connect allows for the reuse of SystemC architectural models as reference models in SystemVerilog verification, and expands the inventory of Verification IP (VIP) by making it easier to integrate off-the-shelf VIP. With the latest enhancement, both UVM and OVM verification teams can maximize their productivity in a mixed-language, mixed-tool environment by using either SystemC or SystemVerilog to implement key pieces of their testbench and provides direct access to UVM and OVM state and control flow from outside SystemVerilog.

Availability

The extensions are available in the updated UVM Connect 2.2 kit. It is available immediately and can be downloaded from the Mentor Verification Academy website: or the Accellera Systems Initiative UVM contributions area . Verification Academy modules on basic and advanced OVM and UVM use, as well as additional training material and online documentation, are also available on the Verification Academy website.

Posted by: John Miklosz