February 19, 2004 -- Electrical engineers are running on Moore's Law's relentless treadmill. Traditionally, Moore's Law says that the number of transistors per chip doubles every 18 months—thanks to advances in photolithography, which allow smaller transistors at higher yields. Its corollary is that the channel length of all gates also decreases. Because the rise time of a gate's transition is proportional to the gate's channel length, rise time, driven by the same forces that drive Moore's Law, decreases with each new generation of chips.
New signal-integrity problems arise as rise times decrease, clock frequencies increase, and designs enter new bandwidth regimes. Many high-speed serial links are now entering the realm in which the transmission-line losses affect signal quality. Products may not work if designers fail to anticipate and minimize these effects to optimize each design.
By Eric Bogatin, PhD and Gene Garat.(Bogatin is chief technology officer at Synergetix, Inc. and Garat is technical marketing engineer for Mentor Graphics HyperLynx product line.)
This brief introduction has been excerpted from the original copyrighted article.