March 04, 2004 -- Now that nanometer technology for ICs is here, the ability to identify and analyze interconnect delays has emerged as a key differentiator in timely closure of successful designs. Interconnect delay is the major component of total delay in all submicron designs and, thus, greatly affects their outcomes.
At these geometries, even familiar closure issues take on new dimensions. In nanometer designs, for example, crosstalk coupling, voltage (IR) drop, and effective loading on the interconnect wires tend to proliferate wildly, producing significant dynamic effects on cell delays.
In addition, wire resistance is increasing at the same time that power supply voltage is decreasing, resulting in designs that are far more susceptible to power supply variations. Hence, the ability to predict IR drop and ground bounce has become essential to effective delay calculation.
By Rahul Deokar. (Deokar is currently the Sr. Product Marketing Manager for Timing and Signal Integrity at Cadence Design Systems, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the eeDesign (EE Times EDA News) website.
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