SynaptiCAD was founded in 1992 to provide high-quality timing diagram editing tools and has since expanded its product line to include VHDL and Verilog test bench generation, timing analysis, stimulus generation, DataBook documentation, and Verilog simulation.

News
WaveFormer Lite Generates Mixed-Signal HDL Test Benches for All FPGA Design Flows	8/11/2010
SynaptiCAD's VeriLogger Supports Encrypted Models from Actel, Altera, and Xilinx	7/1/2010
SynaptiCAD’s 64-Bit Verilog Simulator Now 30% Faster	1/18/2010
SynaptiCAD Offers a Free High-Performance Verilog 2001 Simulator	11/17/2009
Gates-on-the-Fly Netlist Editor Adds Waveform Viewer Interoperability	11/4/2009
SynaptiCAD Tools Import Xilinx Timing Information	9/10/2009
SynaptiCAD Unveils Gates-on-the-Fly Netlist Editor and Schematic Viewer	8/20/2009
SynaptiCAD Offers HDL Works Tools in North America	11/11/2008
Timing Diagram Editors Add Mixed-Signal Capabilities	8/19/2008
SynaptiCAD Acquires Bi-Directional Verilog to VHDL Translation Software; Offers HDL Translation Service	10/17/2007
SynaptiCAD Updates Free Waveform Viewer	5/13/2006
SynaptiCAD Announces Latest Version of Timing Diagram Editor	11/17/2005
SynaptiCAD and Actel Upgrade Libero IDE With Reactive Test Bench Generation	1/31/2005

Articles Online
Easing Today’s Verification Language Bedlam	5/1/2004

Tutorials, White Papers, Conference Papers, etc.

Coding Techniques for Bus Functional Models In Verilog, VHDL, and C++

EDA Tools
Testbencher Pro	Uncategorized
Verilogger Extreme	Uncategorized
Waveformer Pro	Uncategorized

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