Page loading . . .

  
 You are at: The item(s) you requested.Wednesday, May 22, 2013
TransEDA  
Address: PO Box 3556
              Marlborough SN8 9AQ UNITED KINGDOM
Phone: 44 (0 )870 6260631
Email: info@transeda.com
Website: www.transeda.com


TransEDA is a provider of integrated verification solutions for system-on-chip (SoC), application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) designs. The company’s products provide a ready-to-use, structured verification environment that works with existing flows and methodologies.

The company's principal product is the Verification Navigator, an integrated design verification environment with tools that perform application-specific test automation, coverage analysis, dynamic property checking, test suite analysis and configurable HDL checking. TransEDA Foundation Models system level verification IP library provides robust, production-proven models, monitors and properties for popular I/O interfaces and leading processors.

EDA Tools

VN-Cover Coverage Analysis

Code Coverage

VN-Cover Emulator Coverage Analysis for HW Emulation

Code Coverage

VN-Spec Requirement Traceability and Impact Analysis

Design Management

imPROVE-HDL Formal Property Checker

Formal Verification

imPROVE-HPK AHB/APB AMBA Hardware Protocol Verification

Formal Verification

imPROVE-HPK AXI AMBA AXI Hardware Protocol Verification

Formal Verification

imPROVE-HPK OCP Hardware Protocol Verification

Formal Verification

VN-Check Configurable HDL Rule Checking

Formal Verification

imPROVE-TLL Transistor-Level Functional Abstraction

Functional Verification

VN-Optimize Test Suite Analysis and Optimization

Testbench Tools

News

TransEDA Announces PSL Support in Assertain

3/2/2006

TransEDA Announces Availability of Assertain

1/23/2006

TransEDA Unveils Assertain Verification Closure Management Tool

5/30/2005

TransEDA Announces Automatic Verification for AMBA AXI-Based Designs

5/3/2005

TransEDA Introduces Expression Coverability Analysis to Eenhance Coverage Accuracy

2/14/2005

TransEDA Adds SystemVerilog Support and Advanced Rule Checking to Verification Navigator Tool Suite

1/24/2005

TransEDA Announces PCI All-in-One Verification IP and VN-Control 3.0 for PCI Express, PCI-X and PCI Based Designs

9/7/2004

TransEDA Announces VN-Cover Coverability Analysis Option

5/24/2004

TransEDA Expands the Value of Coverage with New VN-Spec Specification Coverage Tool

5/24/2004

TransEDA and EVE Team to Provide Code Coverage for Hardware Verification

2/23/2004


Go directly to TransEDA for more company and product information.

Keywords: TransEDA, EDA, Design Entry and/or Analysis (RTL), HW/SW Co-verification (RTL), Power Analysis & Optimization (RTL), Verilog Simulation (RTL), Test & Verification (ESL),
206/603 1/26/2003 8137 661
Rate this vendor's website (anonymous postings will be deleted)




Designer's Mall
0.46875



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship


Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.546875