Page loading . . .

  
 You are at: The item(s) you requested.Friday, May 24, 2013
Socket-Centric IP Core Interface Maximizes IP Applications  
Company: OCP International Partnership (OCP-IP)
 Printer friendly
 E-Mail Item URL

Semiconductor intellectual property (IP) designers strive to ensure their IP can be utilized by the widest possible range of applications to ensure maximum return on their engineering investment. However, the common older practice of supporting a bus-centric protocol as an IP core’s native interface ultimately limits the market into which an IP core can subsequently be utilized or sold. Fortunately, there is now an optimized and fully-supported interface approach available that utilizes the benefits of the OCP SOCKET.

Access the entire document on the OCP International Partnership (OCP-IP) website.

E-mail OCP International Partnership (OCP-IP) for more information.

Read more about
OCP International Partnership (OCP-IP)
on SOCcentral.com


Keywords: OCP International Partnership (OCP-IP), intellectual property (IP),
205/6104 5/5/2004 4122 838
Add a comment or evaluation (anonymous postings will be deleted)



Designer's Mall
0.265625



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.3125