June 16, 2004 -- Power integrity has become a key design factor for 130nm process technology and below. More and more chip failures are being reported industry-wide, due to I/O cell simultaneous switching output (I/O SSO). As the number of pins increase, the possibility of large supply noise on the chip and in the package due to simultaneous switching outputs increases as well.
Traditionally, the analysis of I/O SSO has been outside of the scope of EDA flows, which typically concentrated on either chip, or on package, or on PCB analysis. Global I/O SSO, however, requires a combined analysis of all these elements, and therefore requires a special methodology tailored to this purpose.
By Margaret Schmitt and Yu Liu. (Liu is the Director of Simulation Products and Schmitt is a senior applications engineer at Apache Design Solutions.)
This brief introduction has been excerpted from the original copyrighted article.