July 09, 2004 -- It is a known fact that functional verification
takes the lion's share of the design cycle. With so many new techniques
available today to alleviate this problem, which techniques should we really
use? The answer, it so happens, is not straightforward and is often confusing
This article gives the reader an overview of the prevalent verification
techniques (formal verification, random, directed, constrained random,
assertions, property checking) and languages (SystemC, C/C++, SystemVerilog,
OpenVera, e). It also examines the place for the various verification techniques
and the time one should use them during a traditional digital ASIC design flow.
By Rangarajan (Sri) Purisai. (Purisai is a senior logic
design engineer at Cypress Semiconductor's Network Processing Solutions
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the eeDesign (EE Times EDA News) website.
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Cypress Semiconductor Corp.