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1 Panel: CEO PANEL: EDA: This is Serious Business
1.1 CEO PANEL: EDA: This is Serious Business
2 Special Session: HOT Leakage
2.1 Circuit and Device Optimizations with Electrothermal Coupling in Scaled Technologies
2.2 Leakage Estimation and Leakage Control for Nano-Scale CMOS Circuits
2.3 System Level Leakage Reduction Considering the Interdependency between Temperature and Leakage
3 Clock Routing and Buffering
3.1 Reducing Clock Skew Variability via Cross Links
3.2 Fast and Flexible Buffer Trees That Navigate the Physical Layout Environment
3.3 Practical Repeater Insertion For Low Power: What Repeater Library Do We Need?
4 Tools and Strategies for Dynamic Verification
4.1 Industrial Experience with Test Generation Languages for Processor Verification
4.2 Defining Coverage Views to Improve Functional Coverage Analysis
4.3 Systematic Functional Coverage Metric Synthesis from Hierarchical Temporal Event Relation Graph
4.4 Probabilistic Regression Suites for Functional Verification
5 Timing-Driven System Synthesis
5.1 Modular Scheduling of Guarded Atomic Actions
5.2 Automatic Correct Scheduling of Control Flow Intensive Behavioral Descriptions in Formal Synthesis
5.3 A Timing-Driven Chip-Level Design Flow
5.4 Timing Closure through a Globally Synchronous Timing Partitioned Design Methodology
6 Special Session: Reliable System-on-a-Chip Design in the Nanometer Era
6.1 Design and Reliability Challenges in Nanometer Technologies
6.2 A Communication-Theoretic Design Paradigm for Reliable SoCs
6.3 Reliable Communication in SoCs
6.4 Designing Robust Microarchitectures
6.5 Hierarchical Application-Aware Error Detection and Recovery
7 Panel: When IC Yield Missed the Target, Who is at Fault?
7.1 When IC yield misses the target, who is at fault?
8 Power Modeling and Optimization for Embedded Systems
8.1 Memory Access Scheduling and Binding Considering Energy Minimization in Multi-Bank Memory Systems
8.2 Profile-Based Optimal Intra-Task Voltage Scheduling for Hard Real-Time Applications
8.3 Requirement-Based Design Methods for Adaptive Communications Links
8.4 Automated Energy/Performance Macromodeling of Embedded Software
8.5 Coding for System-on-Chip Networks: A Unified Framework
9 Performance Evaluation and Run Time Support
9.1 Abstraction of Assembler Programs for Symbolic Worst Case Execution Time Analysis
9.2 Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration
9.3 Specific Scheduling Support to Minimize the Reconfiguration Overhead of Dynamically Reconfigurable Hardware
9.4 LODS: Locality-Oriented Dynamic Scheduling for On-Chip Multiprocessors
9.5 An Area Estimation Methodology for FPGA Based Designs at System-C Level
10 Advances in Analog Circuit and Layout Synthesis
10.1 Automated Design of Operational Transconductance Amplifiers Using Reversed Geometric Programming
10.2 Correct-by-Construction Layout-Centric Retargeting of Large Analog Designs
10.3 Fast and Accurate Parasitic Capacitance Models for Layout-Aware Synthesis of Analog Circuits
10.4 ORACLE: Optimization with Recourse of Analog Circuits Including Layout Extraction
10.5 A Synthesis Flow Toward Fast Parasitic Closure for Radio-Frequency Integrated Circuits
11 Power Grid Design and Analysis Techniques
11.1 Buffer Sizing for Clock Power Minimization Subject to General Skew Constraints
11.2 Optimal Placement of Power Supply Pads and Pins
11.3 A Stochastic Approach to Power Grid Analysis
11.4 Efficient Power/Ground Network Analysis for Power Integrity-Driven Design Methodology
11.5 Reliability-Driven Layout Decompaction for Electromigration Failure Avoidance in Complex Mixed-Signal IC Designs
12 Panel: What Happened to ASIC? Go (Recon)figure?
12.1 What Happened to ASIC? Go (Recon)figure?
13 Methods for a Priori Feasible Layout Generation
13.1 Optical Proximity Correction (OPC)-Friendly Maze Routing
13.2 Design Automation for Mask Programmable Fabrics
13.3 On Designing Via-Configurable Cell Blocks for Regular Fabrics
13.4 Routing Architecture Exploration for Regular Fabrics
13.5 Accurate Estimation of Standard Cell Characteristics
14 Abstraction Techniques for Functional Verification
14.1 An Efficient Finite Domain Constraint Solver for Circuits
14.2 Automatic Abstraction and Verification of Verilog Models
14.3 Abstraction Refinement by Controllability and Cooperativeness Analysis
14.4 Verifying a Gigabit Ethernet Switch Using SMV
14.5 A General Decomposition Strategy for Verifying Register Renaming
15 Memory and Network Optimization in Embedded Designs
15.1 An Integrated Hardware Software Approach for Run-Time Scratchpad-Management
15.2 Multi-Profile Based Code Compression
15.3 An Efficient Scalable and Flexible Data Transfer Architecture for Multiprocessor SoC with Massive Distributed Memory
15.4 Operating-System Controlled Network on Chip
15.5 DyAD - Smart Routing for Networks-on-Chip
16 Special Session: The Future of Timing Closure
16.1 Timing Closure for Low-FO4 Microprocessor Design
16.2 Forest vs. Trees: Where's the Slack?
16.3 Efficient Timing Closure Without Timing Driven Placement and Routing
17 Panel: Verification, What Works and What Doesn't
17.1 Verification, What Works and What Doesn't
18 Design Space Exploration and Scheduling for Embedded Software
18.1 Leakage Aware Dynamic Voltage Scaling for Real-Time Embedded Systems
18.2 Retargetable Profiling for Rapid, Early System Level Design Space Exploration
18.3 High Level Cache Simulation for Heterogeneous Multiprocessors
19 Advances in Accelerated Simulation
19.1 Communication-Efficient Hardware Acceleration for Fast Functional Simulation
19.2 A Fast Hardware/Software Co-Verification Method for System-on-a-Chip by Using a C/C++ Simulator and Emulator with Shared Register Communication
19.3 CircuitAware Architectural Simulation
20 Design for Manufacturability
20.1 Toward a Methodology for Manufacturability Driven Design Rule Exploration
20.2 Phase Correct Routing for Alternating Phase Shift Masks
20.3 Toward a Systematic-Variation Aware Timing Methodology
20.4 Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Control
21 Statistical Timing Analysis
21.1 First-Order Incremental Block-Based Statistical Timing Analysis
21.2 Fast Statistical Timing Analysis with Arbitrary Delay Correlations
21.3 STAC: Statistical Timing Analysis with Correlation
22 Panel: System-Level Design: Six Success Stories in Search of an Industry
22.1 System Level Design: Six Success Stories in Search of an Industry
23 New Ideas in Placement
23.1 Large-Scale Placement by Grid-Warping
23.2 Placement Feedback: A Concept and Method for Better Min-Cut Placements
23.3 Quantum-Dot Cellular Automata Partitioning: Problem Modeling and Solutions
24 Model Order Reduction and Variational Techniques for Parasitic Analysis
24.1 Passivity-Preserving Model Reduction via a Computationally Efficient Project-and-Balance Scheme
24.2 A Linear Fractional Transform (LFT) Based Model for Interconnect Parametric Uncertainty
24.3 Variational Delay Metrics for Interconnect Timing Analysis
24.4 Exploiting Input Information in a Model Reduction Algorithm for Massively Coupled Parasitic Networks
25 Compilation Techniques for Embedded Applications
25.1 Automatic Translation of Software Binaries onto FPGAs
25.2 Area-Efficient Instruction Set Synthesis for Reconfigurable System-on-Chip Designs
25.3 Data Compression for Improving SPM Behavior
26 Special Session: Platform-Based System Design
26.1 Platform Based Design: Does it Answer the Entire SoC Challenge?
26.2 Nomadic Platform Approach for Wireless Mobile Multimedia
26.3 Benefits and Challenges of Platform Based Design
26.4 Trends in the Use of Re-Configurable Platforms
27 Innovations in Logic Synthesis
27.1 A Recursive Paradigm to Solve Boolean Relations
27.2 A Robust Algorithm for Approximate Compatible Observability Don't Care (CODC) Computation
27.3 A Method to Decompose Multiple-Output Logic Functions
27.4 Symmetry Detection for Incompletely Specified Functions
27.5 Implicit Enumeration of Structural Changes in Circuit Optimization
28 Yield Estimation and Optimization
28.1 Parametric Yield Estimation Considering Leakage Variability
28.2 A Methodology to Improve Timing Yield in the Presence of Process Variations
28.3 Novel Sizing Algorithm for Yield Improvement under Process Variation in Nanometer Technology
28.4 Statistical Timing Analysis Based on a Timing Yield Model
29 High-Level Techniques for Signal Processing
29.1 System Design for DSP Applications in Transaction Level Modeling Paradigm
29.2 An Analytical Approach for Dynamic Range Estimation
29.3 Automated Fixed-Point Data-Type Optimization Tool for Signal Processing and Communication Systems
29.4 An Algorithm for Converting Floating-Point Computations to Fixed-Point in MATLAB Based FPGA Design
29.5 Synthesizing Interconnect-Efficient Low Density Parity Check Codes
30 Advanced Test Solutions
30.1 On Path-Based Learning and its Applications in Delay Test and Diagnosis
30.2 Efficient On-Line Testing of FPGAs with Provable Diagnosabilities
30.3 On Test Generation for Transition Faults with Minimized Peak Power Dissipation
30.4 A New State Assignment Technique for Testing and Low Power
30.5 Automatic Generation of Breakpoint Hardware for Silicon Debug
31 Advances in Boolean Analysis Techniques
31.1 AMUSE: A Minimally-Unsatisfiable Subformula Extractor
31.2 A SAT-Based Algorithm for Reparameterization in Symbolic Simulation
31.3 Exploiting Structure in Symmetry Detection for CNF
31.4 Refining the SAT Decision Ordering for Bounded Model Checking
31.5 Efficient Equivalence Checking with Partitions and Hierarchical Cut-Points
32 Panel: Were the Good Old Days all that Good? EDA Then and Now
32.1 Were the Good Old Days all That Good? EDA Then and Now
33 Power Optimization for Real-Time and Media-Rich Embedded Systems
33.1 Off-Chip Latency-Driven Dynamic Voltage and Frequency Scaling for an MPEG Decoding
33.2 Energy-Aware Deterministic Fault Tolerance in Distributed Real-Time Systems
33.3 Proxy-Based Task Partitioning of Watermarking Algorithms for Reducing Energy Consumption in Mobile Devices
33.4 Adaptive Data Partitioning for Ambeint Multimedia
33.5 Energy Characterization of Filesystems for Diskless Embedded Systems
34 Latency Tolerance and Asynchronous Design
34.1 A Method for Correcting the Functionality of a Wire-Pipelined Circuit
34.2 A New Approach to Latency Insensitive Design
34.3 Pre-Layout Wire Length and Congestion Estimation
34.4 The Best of Both Worlds: The Efficient Asynchronous Implementation of Synchronous Specifications
34.5 Fast Hazard Detection in Combinational Circuits
35 New Technologies in System Design
35.1 Defect Tolerant Probabilistic Design Paradigm for Nanotechnologies
35.2 Architecture-Level Synthesis for Automatic Interconnect Pipelining
35.3 Automatic Generation of Equivalent Architecture Model from Functional Specification
35.4 Divide-and-Concatenate: An Architecture Level Optimization Technique for Universal Hash Functions
35.5 Performance Analysis of Different Arbitration Algorithms of the AMBA AHB Bus
36 Special Session: BioMEMS
36.1 Design Tools for BioMEMS
36.2 Atomistic and Multiscale Techniques for Bio-Nano Devices
36.3 CAD Challenges in BioMEMS Design
37 Panel: Will Moore's Law Rule in the Land of Analog?
37.1 Will Moore's Law Rule in the Land of Analog
38 Floorplanning
38.1 Profile-Guided Microarchitectural Floorplanning for Deep Submicron Processor Design
38.2 Floorplanning Optimization with Trajectory Piecewise-Linear Model for Pipelined Interconnects
38.3 A Packing Algorithm for Non-Manhattan Hexagon/Triangle Placement by Using an Adaptive O-Tree Representation
39 Issues in Timing Analysis
39.1 Worst-Case Circuit Delay Taking into Account Power Supply Variations
39.2 Statistical Gate Delay Model Considering Multiple Input Switching
39.3 Static Timing Analysis Using Backward Signal Propagation
40 Special Session: ISSCC Highlights
40.1 Design and Implementation of the POWER5 Microprocessor
40.2 A Dual Core 64b UltraSPARC Microprocessor for Dense Server Applications
40.3 Low-Voltage-Swing Logic Circuits for a Pentium 4 Processor Integer Core
41 Special Session: Multiprocessor SoC MPSoC Solutions/Nightmare
41.1 The Future of Multiprocessor Systems-on-Chips
41.2 Heterogeneous MP-SoC--The Solution to Energy-Efficient Signal Processing
41.3 Flexible Architectures for Engineering Successful MPSoCs
42 Panel: Is Statistical Timing Statistically Significant?
42.1 Is Statistical Timing Statistically Significant?
43 Timing Issues in Placement
43.1 Modeling Repeaters Explicitly within Analytical Placement
43.2 Quadratic Placement Using an Improved Timing Model
43.3 An Approach to Placement-Coupled Logic Replication
44 Design Methodologies for ASIPs
44.1 A Novel Approach for Flexible and Consistent ADL-Driven ASIP Design
44.2 Characterizing Embedded Applications for Instruction-Set Extensible Processors
44.3 Introduction of Local Memory Elements in Instruction Set Extensions
45 FPGA-Based Systems
45.1 FPGA Power Reduction Using Configurable Dual-Vdd
45.2 Multi-Resource Aware Partitioning Algorithms for FPGAs with Heterogeneous Resources
45.3 An SoC Design Methodology Using FPGA and Embedded Microprocessors
46 Special Session: Security as a New Dimension in Embedded System Design
46.1 Security Challenges in Embedded System Design
46.2 Exploiting Embedded Software
46.3 Processor Architectures for Efficient Secure Information Processing
46.4 Attacks and Countermeasures for Tamper-Resistant Embedded Hardware Devices
47 Leakage Power Optimization
47.1 Tradeoffs between Gate Oxide Leakage and Delay for Dual Tox Circuits
47.2 Implicit Pseudo Boolean Enumeration Algorithms for Input Vector Control
47.3 Statistical Optimization of Leakage Power Considering Process Variations Using Dual-Vth and Sizing
47.4 Leakage - and Crosstalk-Aware Bus Encoding for Total Power Reduction
47.5 Power Minimization Using Simultaneous Gate Sizing, Dual-Vdd, and Dual-Vth Assignment
48 Interconnect Extraction
48.1 Sparse Transformations and Preconditioners for Hierarchical 3-D Capacitance Extraction with Multiple Dielectrics
48.2 A Fast Parasitic Extractor Based on Low Rank Multilevel Matrix Compression for Conductor and Dielectric Modeling in Microelectronics and MEMS
48.3 CHIME: Coupled Hierarchical Inductance Model Evaluation
48.4 Large-Scale Full-Wave Simulation
48.5 Closed-Form Expressions of Distributed RLC Interconnects for Analysis of On-Chip Inductance Effects
49 New Frontiers in Logic Synthesis
49.1 Re-Synthesis for Delay Variation Tolerance
49.2 Post-Layout Logic Optimization of Domino Circuits
49.3 Multiple Constant Multiplication by Time-Multiplexed Mapping of Addition Chains
49.4 Decomposing Specifications with Concurrent Outputs to Resolve State Coding Conflicts in Asynchronous Logic Synthesis
49.5 A New Heuristic Algorithm for Reversible Logic Synthesis
49.6 Quantum Logic Synthesis by Symbolic Reachability Analysis
50 Numerical Techniques for Simulation
50.1 A Frequency Relaxation Approach for Analog/RF System-Level Simulation
50.2 Robust, Stable Time-Domain Methods for Solving MPDE of Fast/Slow Systems
50.3 High-Level Simulation of Substrate Noise in High-Ohmic Substrates with Interconnect and Supply Effects
50.4 Hierarchical Approach to Exact Symbolic Analysis of Large Analog Circuits
50.5 An Essentially Non-Oscillatory (ENO) High-Order Accurate Adaptive Table Model for Device Modeling
51 Energy and Thermal-Aware Design
51.1 Theoretical and Practical Limits of Dynamic Voltage Scaling
51.2 Enabling Energy Efficiency in Via-Patterned Gate Array Devices
51.3 Compact Thermal Modeling for Temperature-Aware Design
51.4 Simultaneous Optimization of Supply and Threshold Voltages for Low-Power and High-Performance Circuits in the Leakage Dominant Era
52 Noise-Tolerant Design and Analysis Techniques
52.1 Noise Characterization of Static CMOS Gates
52.2 A Scalable Soft Spot Analysis Methodology for Compound Noise Effects in Nano-Meter Circuits
52.3 A Novel Technique to Improve Noise Immunity of CMOS Dynamic Logic Circuits
52.4 Statistical Timing Analysis in Sequential Circuit for On-Chip Global Interconnect Pipelining
53 New Tools and Methods for Future Embedded SoC
53.1 Debugging HW/SW Interface for MPSoC: Video Encoder System Design Case Study
53.2 SUNMAP: A Tool for Automatic Topology Selection and Generation for NoCs
53.3 FITS: Framework-Based Instruction-Set Tuning Synthesis for Embedded Application Specific Processors
53.4 Mapping a Domain Specific Language to a Platform FPGA
54 New Scan-Based Test Techniques
54.1 On the Generation of Scan-Based Test Sets with Reachable States for Testing under Functional Operation Conditions
54.2 Scalable Selector Architecture for X-Tolerant Deterministic BIST
54.3 Scan-BIST Based on Transition Probabilities
54.4 Combining Dictionary Coding and LFSR Reseeding for Test Data Compression
55 CAD for Reconfigurable Computing
55.1 Virtual Memory Window for Application-Specific Reconfigurable Coprocessors
55.2 Dynamic FPGA Routing for Just-in-Time FPGA Compilation
55.3 An Efficient Algorithm for Finding Empty Space for Online FPGA Placement
100 Business Day: Competitive Strategies for the Electronics Industry
100.1 Globalization -- A Competitive Imperative
100.2 Better, Faster, Cheaper Approaches to Patents: Managing Intellectual Property Strategically and
100.3 Competitive Marketing in an Evolving Electronics World
100.4 Discussion/ Q&A
150 Business Day: Business Models in IP, Software Licensing, and Services
150.1 IP: Who Needs What, and Where They Find It
150.2 Licensing Options: Finding the Win-Win
150.3 Integrated Design/Supply Chain Models to Accelerate Product Development
150.4 Discussion/Q&A
