September 15, 2004 -- While many techniques have evolved to address power minimization during the functional mode of operation, it is also necessary to manage power during the test mode. Circuit activity is substantially higher during test than during functional mode, and the resulting excessive power consumption can increase chip reliability failures due to higher junction temperature and increased peak power.
Today, scan technology is used for integrated circuit (IC) test, which increases the switching activity well beyond that of the normal operation of the IC. This switching activity increases the energy, peak power and average power consumption of the device.
Over the years, numerous techniques for power reduction within the context of "back-end" test have been proposed, focusing on improvements to ATPG algorithms, pattern ordering methods, and scan chain modifications, as well as clocking changes. However, while these techniques have yet to come into mainstream use, the design flow has since adapted to create better power management within the context "front-end" design. These significant advancements in power management have created the need for new power-aware test technology that works throughout the flow.
In this article, we will look at the necessity of having a design flow that incorporates power-aware test. This includes the ability to design for testability and to create test programs for a device within its power limits.
By Cheng Shi and Rohit Kapur. (Shi is Director of Corporate Application Engineering (CAE) for Low Power and Automatic Test-Pattern Generation (ATPG) products within Synopsys' Implementation Group and Kapur is a Synopsys Scientist who guides the development of Synopsys design-for-test (DFT) solutions based on Core Test Language (CTL) and other open standards.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the eeDesign (EE Times EDA News) website.
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