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 Category: EDA/EDA Tools: Wednesday, September 28, 2016
 EDA/EDA Tools is engaged in a major project to build the most comprehensive directory of EDA tools – and EDA tool vendors – available on the Internet. As we add tools to the directory, they'll be highlighted here so if you see a tool that you're not familiar with, take the time to check it out.

The database of EDA tool suppliers includes brief company descriptions and links to their news announcements, articles that have been published online, as well as whitepapers and tutorials available online.

EDA Tool Categories

EDA Tools added to the SOCcentral Directory since Wednesday, September 21, 2016

Tool Name and Vendor


GateVision PRO Netlist Debugging and Viewing (Concept Engineering GmbH)

Viewing & Debugging

Nlview Widgets Automatic Schematic Generation (Concept Engineering GmbH)

Schematic Generation

RTLvision PRO RTL Debugging and Visualization (Concept Engineering GmbH)

Viewing & Debugging

SGvision PRO Gate- and SPICE-Level Visualization and Debugging (Concept Engineering GmbH)

Viewing & Debugging

SpiceVision PRO SPICE Debugging (Concept Engineering GmbH)

Schematic Generation

StarVision PRO Mixed-Signal and Mixed-Language Debugger (Concept Engineering GmbH)

Viewing & Debugging

T-engine Transistor-Level Schematic Generator (Concept Engineering GmbH)

Schematic Generation

SOCcentral has abstracted and indexed a large number of articles, tutorials, white papers, etc. on EDA and EDA tools that are available online. Scroll down for the list of Magazine & Journal articles on EDA , as well as the list of Tutorials, White Papers, etc. on EDA that we've identified. The magazine and journal articles published since January 2010 are accessible from this page, but if you're interested in articles as far as January of 2002, you'll need to go to Articles Online and do a keyword search for a specific year.

Suggested Tutorials, White Papers, Webcasts, etc. on EDA tools

Recently added Tutorials, White Papers, etc. on EDA tools (last 6 weeks)

Designer's Mall

Recent SOCcentral news articles on EDA and EDA tools (last 6 weeks)

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Magazine & Journal articles on EDA and EDA tools

Simulation "Unknowns" and Synthesis "Don't Cares" (Electronic Engineering Times (EE Times)) 11/5/2014
Clock-Domain Crossing Verification: Essentials to Achieve SOC Success (ChipEstimate) 10/28/2014
SOC Verification: Can We Stop the Stampede? (Electronic Engineering Times (EE Times)) 10/9/2014
Test-Cost Challenges in LPCT (Low-Pin-Count Test) Designs (EDN Magazine) 10/7/2014
Trends in Power Supply Packaging: Advances in Component Integration (EDN Magazine) 10/6/2014
Faster Integration Verification for Test Vehicles Using Formal Techniques (EDN Magazine) 9/30/2014
The Evolution of lint (Tech Design Forum) 9/30/2014
Top 5 Things to Know About Wireless Power Design (EDN Magazine) 9/25/2014
Is FPGA Power Design Ready for Concurrent Engineering? (EDN Magazine) 9/24/2014
Managing Power Network Integrity and Voltage Drop in Design Implementation (EDN Magazine) 9/23/2014
Reliable SOC Bus Architecture Improves Performance (EDN Magazine) 9/23/2014
Accurate Compact Thermal Models of Three-Die Power Packages (EDN Magazine) 9/22/2014
Design Faults Leading to Clock and Data Glitches (EDN Magazine) 9/19/2014
Efficiently Estimate and Optimize Leakage in SOCs (EDN Magazine) 9/10/2014
Design Shifts from PCB- to Product-Centric (EDN Magazine) 9/9/2014
Silicon Validation: A Black-Box Approach (EDN Magazine) 9/3/2014
BIST Schemes for ADCs (EDN Magazine) 8/29/2014
Automatically Generated C Test Cases Earn a Solid Return on Investment (Electronic Design Magazine) 8/27/2014
Memory Partitioning and Slack Scheduling Boost Performance in Safety-Critical Applications (Electronic Design Magazine) 8/26/2014
Signal Integrity and Power Integrity in High-Speed Design (EDN Magazine) 8/26/2014
Challenges and Benefits of Low-Power Design Verification with CPF for a Standalone IP (Design & Reuse) 8/25/2014
Intelligent Vt Structuring to Avoid Temperature Inversion for Performance Gain (Design & Reuse) 8/21/2014
C++14 Adds Embedded Features (Electronic Design Magazine) 8/19/2014
Macromodel Extraction Automated Using Spice Netlists (EDN Magazine) 8/17/2014
Macromodel Extraction Automated Using Spice Netlists (EDN Magazine) 8/17/2014
Basics of Multi-Cycle and False Paths (EDN Magazine) 8/7/2014
The Silicon Enigma: Bridging the Gap Between Simulation and Silicon (Design & Reuse) 8/7/2014
GLS Challenges and Solutions with High-Speed Interfaces (EDN Magazine) 8/3/2014
MBIST Verification: Best Practices and Challenges (EDN Magazine) 7/25/2014
Improve Logic Timing with Worst-Case Analysis (Electronic Design Magazine) 7/21/2014
Challenges in LBIST Validation for High-Reliability SOCs (EDN Magazine) 7/19/2014
Apply IEEE 1500 to Integrate Multiple JTAG Chains in SOCs (Electronic Design Magazine) 7/17/2014
Validating and Using the I2C Protocol (EDN Magazine) 7/15/2014
CDC verification of Billion-Gate SOCs (EDN Magazine) 7/13/2014
It's Time to Embrace Objective-Driven Verification (Tech Design Forum) 7/13/2014
SystemVerilog versus SystemC (Design & Reuse) 7/11/2014
Reduce SOC Verification Time Through Reuse in Pre-Silicon Validation (EDN Magazine) 7/9/2014
Pitfalls of State-Transition Clock Gating (EDN Magazine) 7/5/2014
Skillfully Emulating a System-on-Chip (Design & Reuse) 6/30/2014
Optimization Methodologies for Cycle-Accurate SystemC Models Converted from RTL VHDL (Design & Reuse) 6/20/2014
An Effective Way to Drastically Reduce Bug Fixing Time in SOC Verification (Design & Reuse) 6/18/2014
Simplify Analog Circuit Analysis with Impedance and a Signal Flow Graph (EDN Magazine) 6/18/2014
Simplify Analog Circuit Analysis with Impedance and a Signal-Flow Graph (EDN Magazine) 6/18/2014
Hybrid Execution: The Next Step in the Evolution of Hardware-Software Co-Development (EDN Magazine) 6/3/2014
Low-Power Analysis and Verification of Super-Speed Inter-Chip (SSIC) IP (Design & Reuse) 6/2/2014
CPF-Based Verification of an SOC (Design & Reuse) 5/30/2014
Design Rights Management of Intellectual Property (IP) Cores in SoPC Designs (Design & Reuse) 5/18/2014
Seven Benefits of Boundary Scan (EDN Magazine) 5/8/2014
Design Efficiency Metrics Growing Fuzzier (Semiconductor Engineering) 4/24/2014
Does Formal Have You Covered? (Semiconductor Engineering) 4/24/2014
Extending UVM to Analog (Semiconductor Engineering) 4/24/2014
Graphing Toward Standardization (Semiconductor Engineering) 4/24/2014
How to Improve Debug Productivity (Semiconductor Engineering) 4/24/2014
Adding CRC to BIST Improves SOC Safety amd Reliability (EDN Magazine) 4/23/2014
An Intelligent Scan-stitched Architecture for Better ATPG Test Efficiency (EDN Magazine) 4/22/2014
IP Exchange Through Hand-Off for Easy System-on-Chip Design (Design & Reuse) 4/17/2014
Hierarchy Provides a Smarter Approach to SOC CDC Verification (Tech Design Forum) 4/16/2014
Reset Optimization Pays Big Dividends Before Simulation (Tech Design Forum) 4/16/2014
The Case for Rigid-Flex PCB Technology (EDN Magazine) 4/15/2014
A Guide to Advanced Process Design Kits (Semiconductor Engineering) 4/14/2014
What's the Difference Between FPGA and Custom Silicon Emulators? (Electronic Design Magazine) 4/14/2014
Minimize Crosstalk with Optimized PCB Routing Techniques (EDN Magazine) 4/10/2014
SV Assertion-Based Error Signaling Checks and Application Across Popular Bus Protocols (Design & Reuse) 4/10/2014
Development Kits Light Up the Internet of Things (Electronic Design Magazine) 4/9/2014
New Approaches for Reliability (Semiconductor Engineering) 3/28/2014
Distortion Effects Prevail in RF Design (Semiconductor Engineering) 3/27/2014
EDA Shapes Its Future (Semiconductor Engineering) 3/27/2014
Formal Is Set to Overtake Simulation (Semiconductor Engineering) 3/27/2014
How Much Will that Chip Cost? (Semiconductor Engineering) 3/27/2014
Big Shift in SoC Verification (Semiconductor Engineering) 3/17/2014
Overcoming FPGA Board-Design Challenges (EDN Magazine) 3/6/2014
10 Must Knows About Virtual Prototypes (Semiconductor Engineering) 2/27/2014
Abstractions: The Good, Bad and Ugly (Semiconductor Engineering) 2/27/2014
Is Verification at a Crossroads? (Semiconductor Engineering) 2/27/2014
Complexity Drives Smart Reporting (Tech Design Forum) 2/26/2014
The Manual Cost of Managing Open-Source and Third-Party Code (Electronic Design Magazine) 2/19/2014
Software Makes a Difference in Embedded Design (Electronics Weekly) 2/18/2014
Use Embedded Components to Improve PCB Performance and Reduce Size (Electronic Design Magazine) 2/11/2014
Efficient Analysis of CDC Violations in a Million Gate SOC - Part 2 (EDN Magazine) 2/3/2014
How to Speed Up Verification (Semiconductor Engineering) 1/30/2014
The Growing Verification Challenge (Semiconductor Engineering) 1/30/2014
Development Tools Move to the Cloud (Electronic Design Magazine) 1/24/2014
Xilinx Plug-and-Play IP: Accelerating Productivity and Design Reuse (ChipEstimate) 1/21/2014
Efficient Analysis of CDC Violations in a Million Gate SOC - Part 1 (EDN Magazine) 1/17/2014
RTL Synthesis Requirements for Advanced-Node Designs (EDN Magazine) 12/16/2013
Programmable Logic: A Practical Introduction for Beginners (EDN Magazine) 11/19/2013
Intuitive Sampling Theory-Part 4 (EDN Magazine) 10/14/2013
5 Keys for Optimizing SoC Latency and Bandwidth (ChipEstimate) 10/8/2013
Apply Memory BIST to External DRAMs (EDN Magazine) 10/2/2013
SystemC in SOC Development (Design & Reuse) 10/1/2013
Verification Challenges of ADC Subsystem Integration within an SOC (EDN Magazine) 9/30/2013
Reducing Risk in Implementing Technical Computing Algorithms (EDN Magazine) 9/28/2013
Intuitive Sampling Theory-Part 3 (EDN Magazine) 9/27/2013
An Efficient Approach to Evaluate Dynamic and Static Voltage-Drop on a Multi-Million Transistor SOC Design (Design & Reuse) 9/19/2013
Digital Signal Processing Verification (Design & Reuse) 9/19/2013
Middlebrook's Extra Element Theorem (EDN Magazine) 9/15/2013
Bridging the Gap: Pre- to Post-Silicon Functional Validation (Design & Reuse) 9/12/2013
Easier UVM Sequences: SystemVerilog UVM Sequence and Task Equivalence (Design & Reuse) 9/12/2013
Maximizing Test-Stream Coverage of Emerging Standards Like HEVC/H.265 (ChipEstimate) 9/10/2013
Test and Characterize RF Filters in IC Production: A New Approach (EDN Magazine) 9/7/2013
Plan Ahead for a Successful SOC-Based PCB Design (Electronic Design Magazine) 9/5/2013
"Custom Standards" and the Urgent Need for Next-Generation Intellectual Property Share (ChipEstimate) 9/3/2013
Challenges in Power Management Architectures with Internal Regulation (EDN Magazine) 8/28/2013
Open-Source Framework and Practical Considerations for Translating RTL VHDL to SystemC (Design & Reuse) 8/28/2013
Building High-Performance Interrupt Responses into an Embedded SOC Design (EE Times Embedded) 8/25/2013
Extreme Programming (Design & Reuse) 8/22/2013
Comparing Flat ATPG and Hierarchical Tests (EDN Magazine) 8/19/2013
Deriving Design Margins for Successful Timing Closure (EDN Magazine) 8/13/2013
How Reliable Is Your FPGA-based System? (Electronics Weekly) 8/12/2013
Design Planning for Large SOC Implemention at 40nm-Part 3 (EDN Magazine) 8/9/2013
A New Approach to Verifying HDMI (Chip Design Magazine) 8/1/2013
Gate-Level Simulation Resurgence: Is the Answer to Buy a Bigger Hammer? (Chip Design Magazine) 8/1/2013
Why Should We Care About RTL Sign-Off? (Chip Design Magazine) 8/1/2013
A Novel Approach for Improving OCV Impact Earlier in the Design Cycle (Design & Reuse) 7/30/2013
Formal Techniques Tackle the SOC Verification Challenge (Tech Design Forum) 7/25/2013
Low-Power Analog Interface Circuit-Design Techniques for SOCs (Electronic Design Magazine) 7/25/2013
Handling X-Bounding in LBIST Designs (EDN Magazine) 7/23/2013
High-Yield, Low Voltage Multi-Megabit SRAMs with Foundry Bit Cells (ChipEstimate) 7/23/2013
Eliminating Iterations in Gigahertz ASIC Hand-Off (Tech Design Forum) 7/19/2013
10 Tips for Mastering Version-Control Systems (EDN Magazine) 7/16/2013
Are We Too Hard for Agile? (Design & Reuse) 7/16/2013
Clock Gating Logic-Aware Design Closure (Design & Reuse) 7/16/2013
An Insight into Layout versus Schematic (EDN Magazine) 7/15/2013
New Circuit-Board Technologies Meet the Challenge of Digital Power (EDN Magazine) 7/15/2013
Seven Ways to Avoid Embedded PCB Engineering Change Orders (EE Times Embedded) 7/14/2013
Blocking and Non-Blocking RTOS APIs (EE Times Embedded) 7/13/2013
Design Planning for Large SOC Implementation at 40nm-Part 2 (EDN Magazine) 7/12/2013
Hierarchical Physical Design: Issues and Methodologies (EDN Magazine) 7/12/2013
Understanding Low-Power IC Design Techniques (Electronic Design Magazine) 7/11/2013
Using Configurable Processors as Alternatives to FPGAs (EE Times Embedded) 7/8/2013
Basics of Hardware/Firmware Interface Co-Design (EE Times Embedded) 7/7/2013
Simulation: Better than the Real Thing? (EE Times Embedded) 7/6/2013
Design IP Faster: Introducing the C-Flow High-Level Language (Design & Reuse) 7/4/2013
Using Network Standby to Lower Home/Office Device Power Consumption-Part 3 (EE Times Embedded) 7/2/2013
Using Network Standby to Lower Home/Office Device Power Consumption-Part 2 (EE Times Embedded) 7/1/2013
Using Network Standby to Lower Home/Office Device Power Consumption-Part 1 (EE Times Embedded) 6/25/2013
ISS and Architectural Exploration (EE Times EDA Designline) 6/24/2013
Latch-up Improvement for Tap Less Library Through Modified Decoupling Capacitors Cells (Design & Reuse) 6/24/2013
Low-Power Design for Testability (Design & Reuse) 6/20/2013
Test to Avoid Embedded Software Bugs (EDN Magazine) 6/20/2013
Dynamic Memory and Heap Contiguity (EE Times Embedded) 6/16/2013
Reduce SOC Power Consumption without High-Level Circuit-Design Tools (EE Times Embedded) 6/16/2013
A Need for Static and Dynamic Low-Power Verification (Design & Reuse) 6/5/2013
How to Design with finFETs (Tech Design Forum) 5/29/2013
Efficient Physical-Aware Timing ECO Solution (EE Times EDA Designline) 5/27/2013
Facing the Verification-Management Challenge (Tech Design Forum) 5/23/2013
A Generic DDR Behavioural Model (Design & Reuse) 5/22/2013
Address Jitter and Noise More Effectively with DDR4 - Part 1 (EE Times Memory Designline) 5/21/2013
Automated ECO Flow for Overall Cycle-Time Reduction (Design & Reuse) 5/17/2013
Building an RTL Sign-off Flow (Tech Design Forum) 5/14/2013
Power Verification Is Just as Important as Functional Verification for Complex SOCs (New Electronics Magazine) 5/14/2013
Moving to SystemC TLM for Design and Verification of Digital Hardware (EE Times EDA Designline) 5/13/2013
Understanding On-Board Flash Programming (Electronic Design Magazine) 5/10/2013
Eight Requirements for 3D-IC Design (Tech Design Forum) 5/8/2013
Design Planning for Large SOC Implementation at 40nm: Guaranteeing Predictable Schedule and First-Pass Silicon Success (EDN Magazine) 5/7/2013
Design for Manufacturing and Yield (EDN Magazine) 5/6/2013
How to Generate Test Patterns to Detect FinFET Defects (Test & Measurement World) 5/6/2013
Synthesis-Aware Clock Analysis and Constraints Generation (EE Times EDA Designline) 5/6/2013
Physical Verification of finFET and FD-SOI Devices (Tech Design Forum) 5/2/2013
The Power of Developing Hardware and Software in Parallel (Design & Reuse) 5/2/2013
Target Impedance-Based Solutions for Power-Distribution Networks May Not Provide Realistic Assessment (EDN Magazine) 5/1/2013
Tracking Down Interference in Complex RF Environments (EE Times Militray & Aerospace Highlights) 4/30/2013
Boost DFT Efficiency for Large SOCs (Test & Measurement World) 4/23/2013
The Use of FinFETs in IP Design (ChipEstimate) 4/23/2013
FinFET Challenges and Solutions: Custom, Digital, and Sign-Off (EE Times EDA Designline) 4/22/2013
The Five Key Challenges of 20-nm Custom and Analog Design (Tech Design Forum) 4/22/2013
3D-IC Integration: A Stepwise Approach (Tech Design Forum) 4/17/2013
Complex Standards Demand New Approaches to IP Quality (ChipEstimate) 4/16/2013
Small-Signal Simulation in the s-plane (EDN Magazine) 4/15/2013
Stitch and Ship No Longer Viable (EE Times EDA Designline) 4/15/2013
System Test Using JTAG (Design & Reuse) 4/15/2013
Advances in EDA Design Methodologies Led by Next-Generation FPGAs (DSP-FPGA) 4/10/2013
Time to Take Up the 3D-Integration Challenge (Tech Design Forum) 4/10/2013
A Low-Risk, High-Reward Approach to Adopting Formal Methods (EE Times EDA Designline) 4/8/2013
Building Your UVM Verification Environment for Cache-Coherent Interconnects (Design & Reuse) 4/4/2013
Developing Power-Sensitive, Low-Current MCU Designs (EE Times Power Management Designline) 4/4/2013
FPGAs Supercharge Instrument Flexibility (EE Times Programmable Logic Designline) 4/1/2013
Reclaiming Lost Yield Through Methodical Power-Integrity Optimization (EE Times EDA Designline) 4/1/2013
Communication-Centric Test and Debug Infrastructure for Multicore SOCs (Design & Reuse) 3/28/2013
Using Parallel FFT for Multi-Gigahertz FPGA Signal Processing (EE Times Test & Measurement Designline) 3/28/2013
3D Physical Simulation Tools Provide Superior FinFet Predictability (EE Times EDA Designline) 3/25/2013
Dynamic Partitioning Speeds Memory Characterization (EE Times Memory Designline) 3/25/2013
The Challenges of Using Open-Market IP in ASIC Designs (ChipEstimate) 3/19/2013
Smart Decap-Insertion Methodology (Design & Reuse) 3/18/2013
Hardware (and Software) Implications of Endianness in SOC Design ( 3/17/2013
Tensilica Acquisition to Accelerate Cadence Core Strategy (Electronic Engineering Times (EE Times)) 3/13/2013
Design Transition from Sync to Async: Design and Verification Challenges (Design & Reuse) 3/11/2013
Virtual Prototyping Methodology to Boot Linux on the ARM Cortex A15 (EE Times EDA Designline) 3/11/2013
Virtual Prototyping Methodology to Boot Linux on the ARM Cortex A15 (EE Times EDA Designline) 3/11/2013
Optimizing Clock-Tree Distribution in SOCs with Multiple Clock Sinks ( 3/10/2013
Testing HDMI and MHL Interfaces (EE Times Test & Measurement Designline) 3/8/2013
An Introduction to Off-Loading CPUs to FPGAs: Hardware Programming for Software Developers (EE Times Programmable Logic Designline) 3/7/2013
Advanced Yield-Enhancement Technique: Lithography-Friendly Design (EE Times EDA Designline) 3/4/2013
Best Design Practices for High-Capacity FPGA Devices (Electronic News) 3/4/2013
Prototyping Signal Processing and Communications Algorithms on FPGAs Using Model-Based Design (Electronic News) 2/27/2013
State of RTL-based Design: Is It Time to Move Beyond? (Design & Reuse) 2/25/2013
Using 3rd-Party IP in ASIC/SOC Design (EE Times EDA Designline) 2/25/2013
FPGA Design Heads into the Cloud (EE Times Programmable Logic Designline) 2/22/2013
Characterizing Mixed-Signal ICs for Production (EDN Magazine) 2/20/2013
A Practitioner's Guide to Critical-Software Certification (Electronic Design Magazine) 2/11/2013
Guidelines for Early Power Analysis (EE Times EDA Designline) 2/11/2013
The Perfect Storm: How FPGAs, Multicore CPUs, and Graphical Programming Are Changing the Economics of Embedded Design (Electronic News) 2/11/2013
FPGA Debugging Techniques to Speed Pre-Silicon Validation (EDN Magazine) 2/7/2013
Reducing Power in AMD Processor Cores with RTL Clock-Gating Analysis (EE Times EDA Designline) 2/4/2013
The Rise of the Online Circuit-Design Collective (Electronic Design Magazine) 2/4/2013
Accelerated VIP Solves Firmware and Driver Integration and Validation Trade-Offs (Tech Design Forum) 1/31/2013
Multilayer PCB Simulation (Electronic News) 1/31/2013
10 Software Tips for Hardware Engineers (EDN Magazine) 1/28/2013
Developing FPGA Applications for Edition 2 of the IEC 61508 Safety Standard (EE Times Programmable Logic Designline) 1/25/2013
Discover a Better Way to Go from C-Level to Synthesis for SOC Designs (Electronic Design Magazine) 1/25/2013
Verification IP: The Questions You Should Ask (Tech Design Forum) 1/24/2013
An ESD-Efficient, Generic Low-Power Wake-Up Methodology in an SOC (Design & Reuse) 1/23/2013
Sizing up the Verification Problem (Electronic Design Magazine) 1/23/2013
Accelerating Embedded Design with Cloud-Enabled Development Platforms (EDN Magazine) 1/22/2013
Tackling Large-Scale SOC and FPGA Prototyping Debug Challenges (EE Times EDA Designline) 1/21/2013
Get More out of System Architectures (Tech Design Forum) 1/18/2013
An Example Verification Environment for Different Types of Processor Models (Design & Reuse) 1/15/2013
Why USB 3.0 Will Drive SOC Verification in 2013 (ChipEstimate) 1/15/2013
Circuit Reliability Challenges for the Automotive Industry (EE Times EDA Designline) 1/14/2013
Free Online Design, Simulation, Parts Search Tools (EDN Magazine) 1/14/2013
Integrating Large-Capacity Memory in Advanced-Node SOCs (EE Times Memory Designline) 1/14/2013
DO-254: Increasing Verification Coverage by Test (EE Times Militray & Aerospace Highlights) 1/9/2013
The Case for Developing Custom Analog (Design & Reuse) 1/9/2013
The Efficient Implementation of Asynchronous Logic in COTS FPGAs (EE Times Programmable Logic Designline) 1/4/2013
Flexible and Novel Partitioning Strategy for Hierarchical Design (EE Times EDA Designline) 12/27/2012
Seismic Shifts Await EDA in a More-than-Moore World (Electronic Design Magazine) 12/20/2012
Hybrid Execution and Software-Driven Verification Will Emerge in 2013 (Electronic Design Magazine) 12/19/2012
Companies Ramp Up to Move from 20nm to the Next Node in 2013 (Electronic Design Magazine) 12/18/2012
Formal Methods for Power-Aware Verification (EE Times EDA Designline) 12/17/2012
Reduce Power in Chip Designs with Sequential Clock Gating (Electronic Design Magazine) 12/17/2012
Enabling 3D-IC design (Tech Design Forum) 12/12/2012
High-Performance Hardware Models for System Simulation (EE Times EDA Designline) 12/11/2012
Smashing Through the Mobile Device Memory Bottleneck (ChipEstimate) 12/11/2012
More-than-Moore Memory Grows Up (EDN Magazine) 12/9/2012
20-nm Timing Analysis: A Practical and Scalable Approach (Tech Design Forum) 12/6/2012
High-Performance Logic Libraries for Core Hardening (ChipEstimate) 12/4/2012
The Importance of Verifying the Architecture of an SOC Prototyping System (New Electronics Magazine) 12/1/2012
Design Reuse without Verification Reuse Is Useless (EE Times EDA Designline) 11/26/2012
Speeding Power Estimation from Weeks to Hours (EE Times EDA Designline) 11/19/2012
What's the Difference Between Static Analysis of C and C++ vs. Java Programs (Electronic Design Magazine) 11/19/2012
The Shift Left: How Virtual Prototyping Reduces Risk (Tech Design Forum) 11/16/2012
A Novel Approach for Simulation of Digital Circuits Using Levelization (EDN Magazine) 11/15/2012
EDA Vendors Roll Out Advances for 20-nm Design (DSP-FPGA) 11/13/2012
Optimizing Memory Design (EE Times Memory Designline) 11/13/2012
What's the Difference Between de Jure and de Facto Standards? (Electronic Design Magazine) 11/13/2012
Modeling Embedded Designs-Part 2: Modeling Method Examples (EE Times Embedded) 11/8/2012
ARM-Based Android Hardware/Software Design Using Virtual Prototypes-Part 2: Building a Sensor Subsystem (EE Times Embedded) 11/7/2012
SSM Policy Driven System Management Updates SoC Architecture to Meet today's Operation Complexities (ChipEstimate) 11/6/2012
20-nm Test Demands New Design-for-Test and Diagnostic Strategies (Tech Design Forum) 11/5/2012
High-Yield, High-Performance Memory Design (EE Times EDA Designline) 11/5/2012
Embedded S/W Design Reuse: IDEs Are Rising to the Challenge (EE Times MCU Designline) 10/30/2012
Modeling of Embedded Designs-Part 1: Why Model? (EE Times Embedded) 10/30/2012
Will LDE Stand Between You and Your Next Smart Device? (Electronic Design Magazine) 10/30/2012
Electrically-Aware Design Improves Analog/Mixed-Signal Productivity (EE Times EDA Designline) 10/29/2012
ARM-Based Android Hardware/Software Design Using Virtual Prototypes-Part 1: Why Virtualize? (EE Times Embedded) 10/27/2012
Emulation Delivers System-Level Power Verification (Tech Design Forum) 10/26/2012
RTL Analysis for Complex FPGA Designs Using a Grey Cell Methodology (EE Times Programmable Logic Designline) 10/26/2012
Hybrid Approach to Early Validation and SW Bring-Up (Design & Reuse) 10/25/2012
Generate an Interface Rule for Low-Power Consumer Devices (Electronic Design Magazine) 10/24/2012
Better PCB Design Using the Fabricator's View (Tech Design Forum) 10/23/2012
Memory Solution Addressing Power and Security Problems in Embedded Designs (EE Times EDA Designline) 10/22/2012
Understanding 28-nm SOC Design with ARM-Based Cores (Electronic Design Magazine) 10/19/2012
Automated On-the-Fly Verification of Designs Using Detector-Based Methodology (Design & Reuse) 10/18/2012
Regression Testing with Random Tests Cannot Identify Regressions (EE Times EDA Designline) 10/15/2012
A Standard-Cell Architecture to Deal with Signal-Integrity Issues in Deep-Submicron Technologies (Design & Reuse) 10/11/2012
Marketing and Technology Collide in Competitive Chip Design (Electronic Design Magazine) 10/11/2012
Model Your ADCs in Spice-Part 2 (Electronic Design Magazine) 10/10/2012
What's the Deal with SOC Verification? (Electronic Design Magazine) 10/10/2012
How to Develop Z-Wave Devices (EE Times Smart Enery DesignLine) 10/9/2012
How to Test High-speed Memory with Non-Intrusive Embedded Instruments-Part 3 (Test & Measurement World) 10/9/2012
Physical Verification of 20-nm Designs Through Integrated Double-Patterning Analysis and Repair (Tech Design Forum) 10/9/2012
FinFET Structure Design and Variability Analysis Enabled by TCAD (EE Times EDA Designline) 10/8/2012
Improving Hierarchical Custom-IC Signal Planning (Electronic Design Magazine) 10/8/2012
FPGA High-Efficiency, Low-Noise Pulse-Frequency Space-Vector Modulation-Part 1 (EDN Magazine) 10/4/2012
Multicore ARM SOCs Face Cache Coherency Dilemma (ChipEstimate) 10/2/2012
Use PSpice to Verify Feedback Amplifier Stability (Electronic Design Magazine) 10/2/2012
Removing Pessimism and Optimism in Timing Analysis (EE Times EDA Designline) 10/1/2012
Enhancing Verification through a Highly Automated Data Processing Platform (Design & Reuse) 9/26/2012
Designing a Reset-Aware OVM Testbench (EE Times EDA Designline) 9/24/2012
How to Test High-speed Memory with Non-Intrusive Embedded Instruments-Part 2 (Test & Measurement World) 9/23/2012
Floorplanning: Concept, Challenges and Closure (EDN Magazine) 9/19/2012
Moving to Advanced Reliability Verification (Tech Design Forum) 9/14/2012
Critical Tools for 20-nm Design (Tech Design Forum) 9/12/2012
Why IDEs for Hardware Design Fail (EE Times EDA Designline) 9/11/2012
How FPGAs, Multicore CPUs, and Graphical Programming Are Changing Embedded Design (EE Times Embedded) 9/5/2012
How to Test High-speed Memory with Non-Intrusive Embedded Instruments-Part 1 (Test & Measurement World) 9/4/2012
Get Better Emulation Results in Less Time (Electronic Design Magazine) 8/31/2012
Layer-Aware Optimization (EE Times EDA Designline) 8/27/2012
Verifying Embedded Software Functionality-Part 3: Fault Localization, Metrics and Directed Testing (EE Times Embedded) 8/26/2012
Design Workflow Management Enhances SOC Design Quality and Efficiency (EE Times EDA Designline) 8/20/2012
Move to Broader Coverage in SOC Verification Metrics (Electronic Design Magazine) 8/16/2012
Understanding the Concept of X in SOC Design Flow (EDN Magazine) 8/14/2012
The Forgotten SOC Verification Team (EE Times EDA Designline) 8/13/2012
Design, Simulation and Measurement Automation: The Missing Link (Electronic Products & Technology (EP&T)) 8/10/2012
Equations and Impacts of Setup and Hold Time (EDN Magazine) 8/10/2012
Growing Audio Requirements in SOCs (EDN Magazine) 8/7/2012
Verifying Embedded Software Functionality-Part 2: The Power of Dynamic Slicing (EE Times Embedded) 8/7/2012
Designing a Robust Clock Tree Structure (EE Times EDA Designline) 8/6/2012
Verifying Embedded Software Functionality-Part 1: Why It's Necessary (EE Times Embedded) 8/5/2012
Accelerate Embedded Development with Lua (Electronic Design Magazine) 8/2/2012
Breaking Through the Embedded Memory Bottleneck-Part 1 (EE Times Memory Designline) 7/30/2012
Design for Manufacturability: An Overview (Design & Reuse) 7/30/2012
Power Noise Reduction by Optimizing the Dynamic Power Signature of Digital ICs (EE Times EDA Designline) 7/30/2012
Diagnostic and Repair Tools for Embedded Memory Boost SOC Yields (EE Times Memory Designline) 7/23/2012
Power Awareness in RTL Design Analysis (EE Times EDA Designline) 7/23/2012
Developing High-Frequency Integrated Circuits for Test and Measurement (EDN Magazine) 7/19/2012
Dose Mapper: An Advanced System for Correction of Critical Dimension Variations in Deep-Sub-Micron Technologies (Design & Reuse) 7/19/2012
Resolving Timing Mis-Correlation Using Timing Uncertainties (EDN Magazine) 7/19/2012
Implement Abstraction by Encapsulation in SystemC (Electronic Design Magazine) 7/17/2012
Integrated Chip-Package-System Simulation (EDN Magazine) 7/17/2012
Streamlining Design Using Macro Placement Algorithms in Mixed-Signal SOCs (EE Times Embedded) 7/16/2012
Integrating IDE and RTOS for ARM-based Development (EE Times Industrial Control Designline) 7/11/2012
Selecting PCB Materials for High-Frequency Applications (EDN Magazine) 7/11/2012
Prevention, Quality and Other Innovations in Hardware Debug (EE Times EDA Designline) 7/2/2012
Using Java to Deal with Multicore Programming Complexity: Part 2 - Migrating Legacy C/C++ Code to Java (EE Times Embedded) 6/27/2012
Using Java to Deal with Multicore Programming Complexity-Part 3: Using Java with C and C++ for Real-Time Multicore Designs (EE Times Embedded) 6/27/2012
ACE'ing the Verification of a Cache-Coherent System Using UVM (EE Times EDA Designline) 6/25/2012
Software Extends Hardware-in-the-Loop Real-Time Simulation (EE Times Automotive Designline) 6/25/2012
Using Java to Deal with Multicore Programming Complexity-Part 1: How Java Eases Multicore Hardware Demands on Software (EE Times Embedded) 6/24/2012
Electromagnetic Modeling of Three-Dimensional Integrated Circuits (EE Times EDA Designline) 6/18/2012
Model Your ADCs in Spice-Part 1 (Electronic Design Magazine) 6/15/2012
Separate the Hype from the Reality in 3D-ICs (Electronic Design Magazine) 6/15/2012
3D Architecture Implementation (Design & Reuse) 6/11/2012
Remote Analog Design Centers Reflect a New Reality (Electronic Design Magazine) 6/11/2012
Using Requirements Traceability with Model-Driven Development (EE Times Embedded) 6/11/2012
Power-Aware Emulation Tests Power Islands (EE Times EDA Designline) 6/4/2012
Expanding Emulation'S Reach with Virtual Devices (EE Times Embedded) 6/3/2012
Designing Embedded SOCs Using Older Resistive Technologies (EE Times Embedded) 5/30/2012
Pseudo-Hardening in SOC Design (EDN Magazine) 5/25/2012
Efficient GPGPU Programming with OpenCL (New Electronics Magazine) 5/24/2012
Power: A Significant Challenge in EDA Design (EDN Magazine) 5/24/2012
Effective Finger-Pointing: The Art of Modern Yield Analysis (Tech Design Forum) 5/22/2012
FPGA Testing for DO-254 Compliance (EE Times Militray & Aerospace Highlights) 5/22/2012
Intelligent Debug Tools Becoming a Commercial Necessity (New Electronics Magazine) 5/22/2012
Applications and Use of Stage-Based OCV (EE Times EDA Designline) 5/21/2012
Building Better M2M Devices Through Antenna Optimization (EE Times RF & Microwave Designline) 5/21/2012
Where There's a Will… There’s a Way to Better VHDL Verification (Tech Design Forum) 5/21/2012
Decoupled Constraint Modelling: A Design Methodology for Hard Real-Time SOCs (Tech Design Forum) 5/15/2012
Integrating High-Level Synthesis Design into FPGA SOCs with Less Effort and Risk (DSP-FPGA) 5/15/2012
Tool Providers Focus on Improving the Efficiency of FPGA Design (DSP-FPGA) 5/15/2012
Virtual Prototyping Tools Speed Development for FPGAs with ARM-based SOC Subsystems (DSP-FPGA) 5/15/2012
Top 10 Tips for Success with Formal Analysis-Part 3 (EE Times EDA Designline) 5/14/2012
10 Measurements Defining Signal Integrity (EDN Magazine) 5/10/2012
Interconnect Modeling at 20nm: More of the Same or Completely Different? (Electronic Engineering Times (EE Times)) 5/10/2012
A Decision-Tree Approach to Picking the Right Embedded Multicore Software Architecture (EE Times Embedded) 5/9/2012
On-Chip Frequency Measurements Allow for Concurrent, Parallel, and Faster Frequency Measurements (Test & Measurement World) 5/9/2012
Enough of the Sideshows: It's Time for Some Real Advancement in Functional Verification! (Electronic Engineering Times (EE Times)) 5/8/2012
Design for Reliability: The Golden Age of Simulation-Driven Product Design (EE Times EDA Designline) 5/7/2012
Key Methods for Controlling EMC (EE Times Test & Measurement Designline) 5/7/2012
Time Is Money! A Quick Fix for Those Pesky FPGA Design Errors (EE Times Programmable Logic Designline) 5/4/2012
A Digital Design Flow for Differential ECL High-Speed Applications (Design & Reuse) 5/3/2012
Lessons in Developing and Deploying OVM-Compliant VIP (Design & Reuse) 5/3/2012
Verifying Today's SOCs Requires a New Approach (Electronic Engineering Journal) 5/3/2012
Hierarchical Methods for Power-Intent Specification (EE Times EDA Designline) 4/30/2012
A Modeling Approach for Power-Integrity Simulation in 3D-IC Designs (EE Times EDA Designline) 4/27/2012
Reducing EMI by Using Spread Spectrum Techniques (EE Times Planet Analog) 4/27/2012
The Challenge of the Clock Domain Crossing Verification in DO-254 (Design & Reuse) 4/26/2012
2012 Will Be the Year of Power; Again (EE Times EDA Designline) 4/25/2012
Design-for-Power Methodology (EE Times EDA Designline) 4/20/2012
Enabling High-Performance SOCs Through Multi-Die Reuse (Design & Reuse) 4/20/2012
Low Power Is Everywhere (Electronic Engineering Times (EE Times)) 4/18/2012
Design Considerations for Power-Sensitive Embedded Devices (EE Times Embedded) 4/17/2012
Building Predictability into Your Low-Power Design Flow (EE Times EDA Designline) 4/16/2012
SOC Low-Power Verification Requires a Full-Chip Solution (Electronic Engineering Times (EE Times)) 4/13/2012
Automatic C-to-VHDL Testbench Generation Shortens FPGA Development Time (EE Times Programmable Logic Designline) 4/11/2012
Early and Accurate Power Analysis: Myth or Reality? (EE Times EDA Designline) 4/11/2012
Considerations for Writing UPF for a Hierarchical Flow (EE Times EDA Designline) 4/6/2012
Digital/ Mixed-Signal Scopes Address the Data Dilemma (Electronic Design Magazine) 3/29/2012
What's the Difference Between Pre-Layout and Post-Layout PCB Simulation? (Electronic Design Magazine) 3/26/2012
Virtual Platforms and RPB for Faster System Verification (Design & Reuse) 3/22/2012
Building a NAND Flash Controller with High-Level Synthesis (EE Times Memory Designline) 3/19/2012
Test-Driven Development for Embedded C: Why Debug? (EDN Magazine) 3/15/2012
What's the Difference Between Software Development Platforms? (Electronic Design Magazine) 3/14/2012
Density Requirements at 28nm (EE Times EDA Designline) 3/12/2012
Oscilloscope Memory Depth: When Bigger Is Not Always Better (EE Times Test & Measurement Designline) 3/7/2012
Software-Generated BCH As a Way to Solve Challenges of Providing Multiple Configuration IP (Design & Reuse) 3/6/2012
Mixed-Signal IP Design Challenges in 28nm and Beyond (Design & Reuse) 3/1/2012
Tracing Requirements Through to Object-Code Verification (EE Times Embedded) 2/28/2012
AUTOSAR Timing Models Minimize ECU Risks (EE Times Automotive Designline) 2/27/2012
Eight Ways to Improve RF Spurious Performance (EE Times RF & Microwave Designline) 2/27/2012
Entering the Third Epoch of EDA (EE Times EDA Designline) 2/27/2012
Troubleshooting Real-Time Software Issues Using a Logic Analyzer (EE Times Embedded) 2/27/2012
Multicore Networking in Linux User Space with no Performance Overhead (EE Times Embedded) 2/26/2012
Understanding Cell-Aware ATPG and User-Defined Fault Models (Electronic Design Magazine) 2/23/2012
Application Hardware Modeling: Selective Modeling for Early Prediction of Subsystem Performances Through Simulation (Design & Reuse) 2/22/2012
Model-Based Testing of a State-Machine-Based PLC Design (EE Times Embedded) 2/22/2012
Wide I/O Driving 3-D with Through-Silicon Vias (EE Times EDA Designline) 2/22/2012
Top-level Custom Signal Planning and Routing (EE Times EDA Designline) 2/20/2012
How to Build a Self-Checking Testbench (EE Times Programmable Logic Designline) 2/17/2012
Bridging Software and Hardware to Accelerate SOC validation (EE Times Test & Measurement Designline) 2/15/2012
Introduction to Multisource Clock Tree Systems (Electronic Design Magazine) 2/10/2012
Refactoring Hardware Algorithms to Functional Timed SystemC Models (Design & Reuse) 2/9/2012
Fixing Concurrency Defects in Multicore Design (EE Times Embedded) 2/7/2012
Successful Adoption of DFM (EE Times EDA Designline) 2/6/2012
Analog Mixed-Signal Verification Methodology (AMSVM) (Design & Reuse) 1/31/2012
Top 10 Tips for Success with Formal Analysis-Part 2 (EE Times EDA Designline) 1/30/2012
Agile Development of Real-Time Systems (EE Times Embedded) 1/23/2012
Analog Design in the 21st Century: Challenges, Tools, and IC Advances (EDN Magazine) 1/19/2012
Improving SystemVerilog UVM Transaction Recording and Modeling (Design & Reuse) 1/19/2012
The Fast Track to 3D-IC Testing (EE Times EDA Designline) 1/16/2012
Enhancing Verification through a Highly Automated Data Processing Platform (Design & Reuse) 1/11/2012
Formal Techniques for Protocol Verification: A Case Study on Verifying the ARM ACE Protocol (Electronic Design Magazine) 1/11/2012
How Formal MDV Can Eliminate IP Integration Uncertainty (EE Times EDA Designline) 1/9/2012
Co-Design Reliability Relies on Sound Validation Approaches (Electronic Design Magazine) 1/6/2012
The Prototype Comes of Age (EDN Magazine) 1/5/2012
Use Spice to Analyze DRL in an ECG Front-End (EDN Magazine) 1/5/2012
Functional Coverage Analysis for IP Cores and an Approach to Scale Down Overall Simulation Time (Design & Reuse) 1/3/2012
HW/SW Co-development (with Finally Some Emphasis on Software) (EE Times Embedded) 12/29/2011
Automating Design Rule Waivers in SOC IP Reuse (Electronic Design Magazine) 12/27/2011
Virtual Platforms and TLMs Going Mainstream (Electronic Design Magazine) 12/27/2011
Aligning Software Development Teams through Collaborative Design Management (Electronic Design Magazine) 12/22/2011
Reducing Sign-Off Corners to Achieve Faster 40-nm SOC Design Closure (EE Times Embedded) 12/20/2011
Critical Area Analysis and Memory Redundancy (EE Times EDA Designline) 12/19/2011
Automated Architecture Checking of UML Based SoC Specifications (Electronic Design Magazine) 12/15/2011
Combining Prototyping Solutions to Solve Hardware/ Software Integration Challenges (EE Times EDA Designline) 12/13/2011
Taking Advantage of the Cortex-M3's Pre-Emptive Context Switches (EE Times Embedded) 12/13/2011
Top 10 Tips for Success with Formal Analysis-Part 1 (EE Times EDA Designline) 12/12/2011
Dealing with Multi-Vt and Multi-Voltage Domain Timing/ Temperature Inversion Challenges (EE Times Embedded) 12/7/2011
Virtual Versus Physical Prototyping: Get It Right Faster (EE Times EDA Designline) 11/28/2011
Validating Embedded Flash Memory Products to Endure Power Faults (EE Times Memory Designline) 11/25/2011
System Performance Analysis and Software Optimization Using a TLM Virtual Platform (EE Times EDA Designline) 11/22/2011
Building 3D-ICs: Tool Flow and Design Software - Part 2 (EE Times EDA Designline) 11/21/2011
Design Femtoampere Circuits with Low Leakage - Part 1 (EDN Magazine) 11/17/2011
Building 3D-ICs: Tool Flow and Design Software - Part 1 (EE Times EDA Designline) 11/14/2011
The Limits of Testing in Safe Systems (Electronic Design Magazine) 11/11/2011
Overcoming 40G/100G SerDes Design And Implementation Challenges (EE Times EDA Designline) 11/2/2011
Assertion-Based Verification Benefits FPGA designs (Dataweek) 10/26/2011
In-Target Embedded Software Testing Technology (Dataweek) 10/26/2011
Open Standards Are Better than Open Source (Electronics Weekly) 10/26/2011
Simple Ways to Manage Different Clock Frequencies of Audio Codecs (EE Times Audio Designline) 10/26/2011
Automated On-the-Fly Verification of Designs Using Detector-Based Methodology (Design & Reuse) 10/19/2011
Integrated Tools Streamline Low-Energy MCU Development (EE Times MCU Designline) 10/18/2011
Assertion-Based Verification in Mixed-Signal Design (EE Times EDA Designline) 10/17/2011
Addressing the New Challenges of ASIC/ SOC Prototyping with FPGAs (EE Times Programmable Logic Designline) 10/12/2011
FPGA Functional Verification: Why Bother? (Electronics Weekly) 10/11/2011
Agile Hardware Development: Nonsense or Necessity? (EE Times EDA Designline) 10/10/2011
Static Formal Verification for System-Level Verification (Design & Reuse) 10/7/2011
Meet the SerDes Challenge: Designing a High-Speed Serial Backplane (EE Times RF & Microwave Designline) 10/6/2011
Understanding and Comparing the Differences in ESD Testing (EDN Magazine) 10/6/2011
Reducing Turnaround Time with Hierarchical Timing Analysis (EE Times EDA Designline) 10/3/2011
Minimizing Yield Fallout by Avoiding Over and Under At-Speed Testing (EE Times Embedded) 9/30/2011
Concurrency Checkers Can Improve Multicore Process Performance (New Electronics Magazine) 9/27/2011
Metrix-Driven Hardware/ Software System-Level Verification (Design & Reuse) 9/27/2011
A Practical Approach to IP Quality Inspection (EE Times EDA Designline) 9/26/2011
Dealing with the Pains of Technology Adoption (Electronic Design Magazine) 9/26/2011
Problems and Pitfalls with Signal Integrity at 10Gbps and Beyond (EE Times Planet Analog) 9/23/2011
Latches and Timing Closure: A Mixed Bag (EDN Magazine) 9/22/2011
Partial Reconfiguration in FPGA Rapid Prototyping Tools (Design & Reuse) 9/22/2011
Un-Rolling with the Times (Electronic Engineering Journal) 9/22/2011
How to Test 3D Chips (Electronics Weekly) 9/21/2011
A New Approach to Hardware Design Project Management (EE Times EDA Designline) 9/20/2011
In-Target Embedded Software Test Automation and Quality (EE Times MCU Designline) 9/19/2011
Managing IP Quality in the SOC Era Requires a Purpose-Built DM Approach (Electronic Engineering Times (EE Times)) 9/19/2011
Use Thermal Analysis and Other Types of Simulation to Craft a "Cool" Design (Electronic Design Magazine) 9/16/2011
5 Wirebond Power Bus Watch-Outs! (Design & Reuse) 9/15/2011
Anatomy of a Software Code Audit Process (Electronic Engineering Journal) 9/15/2011
3D-IC Design: The Challenges of 2.5D versus 3D (EE Times EDA Designline) 9/14/2011
APIdeology: Application Programming Interface Best Practices (EE Times Embedded) 9/14/2011
Hunting Noise Sources in Wireless Embedded Systems (EE Times Test & Measurement Designline) 9/14/2011
Design Flow Developments Enable More-Capable Signal Processing (New Electronics Magazine) 9/13/2011
Cell-Aware Fault Models for IC Production Test Outperform Gate-Exhaustive Fault Models (Electronic Engineering Journal) 9/8/2011
Chip-and-Package Co-Design Relieves Pressure on Complex Designs (EDN Magazine) 9/8/2011
Verifying Certified Software: Making the Most of the Tools You Have (EE Times Embedded) 9/6/2011
Breaking the Language Barriers: Using Coverage Driven Verification to Improve the Quality of IP (Design & Reuse) 9/1/2011
Slack Scheduling Enhances Multicore Performance in Safety-Critical Applications (EDN Magazine) 8/25/2011
Developing Processor-Compatible C-Code for FPGA Hardware Acceleration (EE Times Embedded) 8/21/2011
Basics of Core-Based FPGA Design-Part 1: Core Types & Trade-Offs (EE Times Embedded) 8/17/2011
Cache-Coherence Verification (EE Times EDA Designline) 8/17/2011
Making Embedded Processing Development Easy-Part 2 (EE Times MCU Designline) 8/15/2011
Standardization in Software Tools Boosts Development of Next-Generation Applications (EE Times MCU Designline) 8/15/2011
EMI Scans Verify Chip Design and Accelerate Time-to-Market (EE Times Automotive Designline) 8/11/2011
Realizing the Promise of Electrically-Aware Custom IC Design (Electronic Design Magazine) 8/9/2011
Making Embedded Processing Development Easy-Part 1 (EE Times MCU Designline) 8/8/2011
Rapid Design and Protoyping of Proportional-Integral-Derivative (PID) Controllers (EE Times EDA Designline) 8/8/2011
Minimize Leakage Power in Embedded SOC Designs with Multi-Vt Cells (EE Times Embedded) 8/6/2011
An Efficient ASIP Design Methodology (Design & Reuse) 8/4/2011
Marrying Flexibility and Complexity Verifying a DSP in an FPGA (Electronic Engineering Journal) 8/4/2011
Latches and Timing Closure: A Mixed Bag (EE Times EDA Designline) 8/2/2011
Determine the Best Verification Solution for the Task (Chip Design Magazine) 8/1/2011
Routing Technologies for 28nm and Beyond (Chip Design Magazine) 8/1/2011
SOC Ecosystems Become More Tightly Integrated (Chip Design Magazine) 8/1/2011
Tying Software Together to Build Multicore Apps (Electronic Products Magazine) 8/1/2011
Transforming Circuit Board Design Reduces Cost and Risk (Electronic Products Magazine) 7/29/2011
Methods of Estimating Component Temperatures-Part 3: Board Temperature (Electronic Engineering Journal) 7/28/2011
Thermal Analysis and Other Simulation Types (Electronic Design Magazine) 7/27/2011
Take Chip Package Co-Design Modeling from Concept to System Qualification (Electronic Design Magazine) 7/26/2011
3D's Supporting Players (Electronic Engineering Journal) 7/25/2011
Guide to VHDL for embedded software developers-Part 3: ALU Logic and FSMs (EE Times Embedded) 7/25/2011
Making Your Application Code Multicore Ready (EE Times Embedded) 7/25/2011
Migrating from Proprietary to Linux (Open) Development Platforms (EE Times Embedded) 7/25/2011
Methods of Estimating Component Temperatures-Part 2: Case Temperature (Electronic Engineering Journal) 7/21/2011
A Guide to VHDL for Embedded Software Developers-Part 1: Essential Commands (EE Times Embedded) 7/19/2011
Essential Principles for Practical Analog BIST (EE Times Test & Measurement Designline) 7/19/2011
Guide to VHDL for embedded software developers-Part 2: More Essential Commands (EE Times Embedded) 7/19/2011
Managing Signal Integrity in Tomorrow's High-Speed Flash-Memory-System Designs (EE Times Test & Measurement Designline) 7/19/2011
Methods of Estimating Component Temperatures-Part 1 (Electronic Engineering Journal) 7/14/2011
Power-Integrity Simulation Keeps Your Planes Perfect (EDN Magazine) 7/14/2011
Simulation Techniques Test Automotive Cluster Display ECUs (EE Times Automotive Designline) 7/14/2011
How to Accelerate Genomic Sequence Alignment 4X Using Half an FPGA (EE Times Programmable Logic Designline) 7/5/2011
The Quandary of EDA Software Piracy (EDN Magazine) 7/5/2011
Are We Ready for Physical Verification Standards? (Electronic Design Magazine) 6/30/2011
Power Optimization for Low-Power SOCs Targeting Mobile Devices (New Electronics Magazine) 6/29/2011
Creating an SOC Virtual Platform for Embedded Software Development (Electronic Design Magazine) 6/28/2011
Breaking the Language Barriers: Using Coverage Driven Verification to Improve the Quality of IP (Design & Reuse) 6/20/2011
Enhancing Simulation Studies with 3D Animation (EE Times EDA Designline) 6/8/2011
3-D IC Design: New Possibilities for the Wireless Market (EE Times EDA Designline) 6/7/2011
Software Driven Verification (Design & Reuse) 6/2/2011
High-Productivity Design Tools for Custom Analog ICs (Electronic Products Magazine) 6/1/2011
Verifying Designs Before Committing to Hardware (Electronic Products Magazine) 6/1/2011
Two Methodologies for ASIC Conversion (EE Times EDA Designline) 5/31/2011
Guidelines for SystemC: Debugger Integration (Design & Reuse) 5/26/2011
It's Not Just About Hardware Anymore (EE Times Embedded) 5/25/2011
Achieve your SOC Design Goals: Measure Twice, Cut Once! (EE Times EDA Designline) 5/23/2011
Speeding Verification of FPGA-Based Prototype Boards with the ProtoLink Probe Visualizer (EE Times Programmable Logic Designline) 5/23/2011
VMM-Based Multi-Layer Framework for System-Level Verification (EE Times EDA Designline) 5/23/2011
Advanced Power Management in Embedded Memory Subsystems (Design & Reuse) 5/19/2011
Overcoming the Challenges of Formal Verification and Debug (EE Times EDA Designline) 5/18/2011
Time to Exploit IDEs for Hardware Design And Verification (EE Times EDA Designline) 5/18/2011
Design Optimization of Flip-Chip Packages Integrating USB 3.0 (EE Times EDA Designline) 5/11/2011
How to Build a Fast, Custom FFT from C (EE Times Programmable Logic Designline) 5/11/2011
Guidelines for Successful SoC Verification in OVM/UVM (Design & Reuse) 5/10/2011
Optimize Data Flow Video Apps By Tightly Coupling ARM-Based CPUs-to-FPGA Fabrics (EE Times Embedded) 5/10/2011
Platforms Continuum for System Realization (Embedded Computing Design) 5/5/2011
TLM 2.0 Standard into Action: Designing Efficient Processor Simulators (Design & Reuse) 5/5/2011
Debugging for Antenna Issues in Copper Processes (EE Times EDA Designline) 5/4/2011
Developing the World'S First Real-Time 3D OCT Medical Imaging System with NI FlexRIO (EE Times Programmable Logic Designline) 4/26/2011
Cache Evaluation Software: A Dynamically Configurable Cache Simulator (Design & Reuse) 4/21/2011
Plan Strategies for Adopting Model-Based Design for Embedded Applications: Part 4 - Implementation, Verification and Validation (EE Times Automotive Designline) 4/21/2011
Systematic Approach to Verification of a Mixed-Signal IP: HSIC PHY Case Study (Design & Reuse) 4/21/2011
Facilitating At-Speed Test at RTL: Part 2 (EE Times EDA Designline) 4/20/2011
Achieving CDC Verification in the Billion-Transistor Chip Era (Electronic Design Magazine) 4/19/2011
Using Verification Coverage with Formal Analysis (EE Times EDA Designline) 4/13/2011
Facilitating At-Speed Test at RTL: Part 1 (EE Times EDA Designline) 4/12/2011
Analyzing Multithreaded Applications: Identifying Performance Bottlenecks on Multicore Systems (EE Times Embedded) 4/7/2011
Implementing Different Power Features in an IP (Design & Reuse) 4/7/2011
Innovative Circuit Designs Target Performance Improvement and Differentiation (EDN Magazine) 4/7/2011
The 3-D IC and You (EDN Magazine) 4/7/2011
System Level Debugging: A Means to Achieve Holistic Debugging (EE Times EDA Designline) 4/6/2011
How to Achieve Quality Assurance for Your Electronic Designs (EE Times Programmable Logic Designline) 4/4/2011
Analog Circuits Benefit from Scaling Trends (Chip Design Magazine) 4/1/2011
EDA Tools for 3D IC Design (Chip Design Magazine) 4/1/2011
Get the Lowdown on Accellera's VIP and UVM (Chip Design Magazine) 4/1/2011
In IP We Trust? (Chip Design Magazine) 4/1/2011
System-Level Design: Five Likely 2011 Trends (Chip Design Magazine) 4/1/2011
The (Design) House Always Wins: How DFM Improves the Odds of Tape-Out Success (Chip Design Magazine) 4/1/2011
The Missing Pieces in Power Modeling; Who's Going to Provide Them (Chip Design Magazine) 4/1/2011
Automating Design Rule Waivers in SOC IP Reuse (Design & Reuse) 3/31/2011
Attofarad Accuracy for High-Performance Memory Design (EE Times EDA Designline) 3/30/2011
The Challenges and Benefits of Analog/ Mixed-Signal and RF System Verification Above the Transistor Level (Design & Reuse) 3/24/2011
Plan Strategies for Adopting Model-Based Design for Embedded Applications: Part 3 - Migration Plan Requirements and the Design Phase (EE Times Automotive Designline) 3/23/2011
Using Simulation and Emulation Together to Create Complex SOCs (EE Times EDA Designline) 3/23/2011
Analog IP for Multimedia SOCs: An Eye on a World of Essential Analog Features (EE Times Planet Analog) 3/22/2011
Breaking Barriers with FPGA-Based Design-for-Prototyping (XCell Journal Online) 3/22/2011
The Real Role of EDA in the Cloud (EE Times Programmable Logic Designline) 3/22/2011
When It Comes to Runtime Chatter, Less Is Best (XCell Journal Online) 3/22/2011
Time-Domain Simulations of High-speed Links with X Parameters (EE Times RF & Microwave Designline) 3/21/2011
What Makes an Optimal SOC Verification Strategy (EE Times EDA Designline) 3/21/2011
System Awareness Improves SOC Power Management (EE Times Power Management Designline) 3/18/2011
A 55-nm Ultra-Low-Leakage SRAM Compiler with Optimized Power-Gating Design (Design & Reuse) 3/17/2011
Complete IC Simulation Requires a Full Toolbox of Hardware and Software (EDN Magazine) 3/17/2011
Verification of USB 3.0 Device IP Core in Multi-Layer SystemC Verification Environment (Design & Reuse) 3/17/2011
Tracing Mixed-Tool Flows Graphically (EE Times EDA Designline) 3/16/2011
Treat ICs, Packages, and PCBs as System Designs (Electronic Design Magazine) 3/16/2011
Hardware/Software Integration: Closing the Gap (EE Times EDA Designline) 3/13/2011
The Traditional Approach to IC Implementation and Its Problems (Electronic Design Magazine) 3/11/2011
Hardware Co-Verification Using VMM HAL-SCEMI (Design & Reuse) 3/10/2011
Introduction to SVA Assertions for Design Engineers (Design & Reuse) 3/10/2011
Planning Reset Strategy: Flow and Functionality in OVC (EE Times EDA Designline) 3/9/2011
Major Changes Expected for Physical Verification Tools as Designs Move into 28nm and Below (Electronic Engineering Times (EE Times)) 3/8/2011
Evolution of Manufacturing Closure for Advanced Nodes: Part 3 (EE Times EDA Designline) 3/7/2011
How Many-Core Will Reshape EDA (EE Times MCU Designline) 3/7/2011
Which Design Comes First: Hardware or Software? (Electronic Design Magazine) 3/7/2011
Build Accurate Spice Models for Low-noise, Low-Power Precision Amplifiers (EDN Magazine) 3/3/2011
Plan Strategies for Adopting Model-Based Design for Embedded Applications: Part 2 - Strategy for Change (EE Times Automotive Designline) 3/3/2011
Expediting Processor Verification Through Testbench Infrastructure Reuse (EE Times EDA Designline) 3/2/2011
Evolution of Manufacturing Closure for Advanced Nodes: Part 2 (EE Times EDA Designline) 2/28/2011
Plan Strategies for Adopting Model-Based Design for Embedded Applications: Part 1 - Challenges and Impact (EE Times Automotive DesignLine) 2/24/2011
Evolution of Manufacturing Closure for Advanced Nodes: Part 1 (EE Times EDA Designline) 2/21/2011
Hardware Solutions to the Challenges of Multimedia IP Functional Verification (Design & Reuse) 2/16/2011
Ease Production at 65nm with DFM (EE Times EDA Designline) 2/15/2011
Automatic Shape-Based Routing to Achieve Parasitic Constraint Closure in Custom Design (EE Times EDA Designline) 2/9/2011
Compute a Histogram in an FPGA with One Clock (EDN Magazine) 2/3/2011
Lowering the Cost of Medical-Imaging R&D (EDN Magazine) 2/3/2011
ESL Anyone? (EE Times EDA Designline) 2/2/2011
Using SystemC to Build a System-on-Chip Platform (EE Times Embedded) 2/2/2011
Achieving First-Day Multicore SOC Software Success (EE Times Embedded) 2/1/2011
Top 10 EMC Design Considerations (Electronic Products Magazine) 2/1/2011
Design Considerations in the Analog Signal Chain: Part 1 (EE Times Planet Analog) 1/30/2011
2D Integrated Circuits (DAC Knowledge Center) 1/26/2011
How to Instrument Your Design with Simple SystemVerilog Assertions (EE Times EDA Designline) 1/26/2011
The Next Roadblock to Custom Design Productivity: Design Constraints (DAC Knowledge Center) 1/25/2011
Verifying Complex Clock and Reset Regimes in Modern Chips: The Challenge and Scalable Solutions (EDN Magazine) 1/24/2011
Free I/O: Improving FPGA Clock Distribution Control (EE Times Programmable Logic Designline) 1/23/2011
Managing Coverage Grading in Complex Multicore Microprocessor Environments (EE Times EDA Designline) 1/19/2011
Meeting Timing Specs on Boards with Picoseconds of Margin (EE Times Signal Processing DesignLine) 1/19/2011
Packaging Faces a "Perfect Storm" (Electronic Products Magazine) 1/19/2011
Using Co-Design to Optimize System Interconnect Paths (EE Times Embedded) 1/16/2011
Mixed-Signal Designs: The Benefits of Digital Control of Analog Signal Chains (EE Times Planet Analog) 1/15/2011
Using PSpice to Analyze Amplifier Loop Stability: Part 2 (EE Times Planet Analog) 1/13/2011
An RTL-to-GDSII Approach for Low Power Design: A Design for Power Methodology (EE Times EDA Designline) 1/12/2011
How an Emerging Methodology Better Supports SOC Design (Electronic Design Magazine) 1/11/2011
Debugging for Power Consumption (New Electronics Magazine) 1/10/2011
Using PSpice to Analyze Amplifier Loop Stability: Part 1 (EE Times Planet Analog) 1/8/2011
Using Enhanced Triggering to Verify and Debug Complex Designs (EDN Magazine) 1/6/2011
Dawn at the OASIS (DAC Knowledge Center) 1/5/2011
Intelligently Integrated Physical Design and Verification Eliminate Late-Stage Surprises and Manual Fixes (EE Times EDA Designline) 1/5/2011
Verification Challenges and eDFM in Digital Designs (DAC Knowledge Center) 1/5/2011
Death to the DRC Waiver Productivity Tax! (Electronic Design Magazine) 1/4/2011
When Perfect Is Good Enough (Electronic Engineering Times (EE Times)) 1/4/2011
Critical False-Path Analysis Through Sensitization Methods (EDN Magazine) 12/29/2010
FMEA Eases Automotive ASIC Design and Deployment (EE Times Automotive Designline) 12/22/2010
Multiphysics Simulation Enhances Electronics System Design (EDN Magazine) 12/15/2010
The War Is Over: C++ and SystemC Coexist In a Single Flow (EE Times EDA Designline) 12/15/2010
Validate Hardware/ Software for Nextgen Mobile/ Consumer Apps Using System Development Tools (EE Times Embedded) 12/14/2010
Choosing an Effective Embedded SOC ASIC Design Strategy (EE Times Embedded) 12/13/2010
Building FPGA-Based Digital Downconverters With Graphical Design Tools (EE Times Programmable Logic Designline) 12/8/2010
Analog Design Quality Closure: What's Missing from Current Flows? (EE Times EDA Designline) 12/6/2010
Tips About Printed Circuit Board Design: Part 1 - Dealing With Harmful PCB Effects (EE Times Embedded) 12/6/2010
ABQ: Assertion Based Qualifier Methodology for Pre-Existing Environments (Design & Reuse) 12/2/2010
SOC-PLL Design Requires Trade-Offs (EDN Magazine) 12/2/2010
Can You Afford to Ignore Formal Analysis? (EE Times EDA Designline) 11/30/2010
A Methodology for Describing Analog/ Mixed-Signal Blocks as IP (Design & Reuse) 11/25/2010
Guidelines for Verilog-A Compact Model Coding (Design & Reuse) 11/25/2010
The Evolution of Design Methodology (Electronic Engineering Times (EE Times)) 11/24/2010
High-Level Synthesis: Ready for Prime Time? (EE Times EDA Designline) 11/23/2010
Trace-Based Approach for Unit-Level Debug and Verification of C/C++ IP Models (Design & Reuse) 11/18/2010
New IC Verification Techniques for Analog Content (EE Times EDA Designline) 11/17/2010
SOC DFT Verification With Static Analysis and Formal Methods (Test & Measurement World) 11/17/2010
Metric-Driven Validation, Verification and Test of Embedded Software (Design & Reuse) 11/10/2010
Parametric yield: Do You Know What You Miss? (EE Times EDA Designline) 11/10/2010
Essential Principles for Practical Analog BIST (EDN Magazine) 11/4/2010
A Developer's Insight Into ARM Cortex-M Debugging (EE Times Embedded) 11/3/2010
A Next-Gen FPGA-Based SOC Verification Platform (EE Times Programmable Logic Designline) 11/1/2010
Software Update Methods for Android-Based Devices (Electronic Products Magazine) 11/1/2010
The Future of IC Design Verification (Electronic Products Magazine) 11/1/2010
Understanding System-Level Energy-Management Techniques and Test (EDN Magazine) 11/1/2010
Restoring the Artistry of Analog Design (EE Times EDA Designline) 10/26/2010
How to Reduce Board Management Costs, Failures, and Design Time (EE Times Programmable Logic Designline) 10/25/2010
The Advantages of Multi-Rate Harmonic Balance Technology (EE Times RF & Microwave Designline) 10/25/2010
The Case of the Disappearing PCell (EE Times EDA Designline) 10/25/2010
What Can Be Expected from the Accellera Unified Coverage Interoperability Standard? (Electronic Design Magazine) 10/22/2010
Design Environment for the Support of Configurable Network Interfaces in NoC-based Platforms (Design & Reuse) 10/21/2010
Are Design and Test Conflicting or Symbiotic? (Electronic Engineering Times (EE Times)) 10/20/2010
EDA's Next Step: System-Level Design Automation (Electronic Design Magazine) 10/20/2010
Is Your System Ready for 25Gbps? (Electronic Products Magazine) 10/1/2010
Hunting that Elusive Bug (EE Times EDA Designline) 9/28/2010
What! How Big Did You Say That FPGA Is? (EE Times Programmable Logic Designline) 9/27/2010
Using the Application Modeling and Mapping Methodology for System-level Performance Analysis (EE Times Embedded) 9/26/2010
Partial Reconfiguration In FPGA Rapid Prototyping Tools (Design & Reuse) 9/17/2010
Performance Verification of a Complex Bus Arbiter Using the VMM Performance Analyzer (EE Times EDA Designline) 9/16/2010
Accelerating the Development of TLM-2.0 Models Using Model Authoring Kits (MAKs) (Design & Reuse) 9/13/2010
Development Tool Evolution: Hardware/ Firmware (EE Times Programmable Logic Designline) 9/13/2010
Discovering the Last Unrealized Power Reduction (EDN Magazine) 9/13/2010
Do We Need an International EDA Roadmap? (EE Times EDA Designline) 9/13/2010
Debugging the Linux Kernel With JTAG ( 8/31/2010
Optimizing the Manufacturing Test Program, Data Collection, and Diagnosis for Yield Analysis (EE Times EDA Designline) 8/31/2010
Reusable Device Simulation Models for Embedded System Virtual Platforms (Design & Reuse) 8/24/2010
SystemVerilog Configurable Coverage Model In an OVM setup: Concept of Reusability (EE Times EDA Designline) 8/24/2010
An Efficient ASIP Design Methodology (Design & Reuse) 8/16/2010
Comparing AMBA AHB to AXI Bus Using System Modeling (Design & Reuse) 8/16/2010
Data Storage Yields Increased Design Productivity (EDN Magazine) 8/16/2010
FPGA Compilation On-Site or In the Cloud (EE Times Programmable Logic Designline) 8/16/2010
Picking the Right Built-In Self-test Strategy for Your Embedded ASIC (EE Times Embedded) 8/16/2010
Reduce Embedded SOC Design Cost and Optimize IP Integration (EE Times Embedded) 8/16/2010
Transaction Analysis and Debug Across Language Boundaries and Between Abstraction Levels (Design & Reuse) 8/16/2010
Using In-Design Physical Verification to Reduce Tape-Out Schedules (Design & Reuse) 8/2/2010
Use XML to Build ASIC or SOC Design Specifications (EE Times Embedded) 7/31/2010
Design Quality and Its Impact On Design Closure (EDN Magazine) 7/30/2010
EM Simulation for EMC: Keeping a Lid on Interference (EDN Magazine) 7/30/2010
ESL Synthesis: Tips for Implementing a Viable ESL-Synthesis Flow (EDN Magazine) 7/30/2010
Protect Your goal with Post-Silicon Formal Verification (Design & Reuse) 7/30/2010
Accelerating the Time to IC Layout (EE Times EDA Designline) 7/29/2010
Customized FPGA board for ASIC Prototyping: A Novel Approach with Pre-designed Blocks and Modular FPGA (Design & Reuse) 7/29/2010
Generating AMD Microcode Stimuli Using VCS Constraint Solver (Design & Reuse) 7/29/2010
IP Re-Engineering and Design Methodology (Design & Reuse) 7/29/2010
Interoperable DRC/LVS Language Standard Accelerates Physical Verification Turnaround Time for Advanced Nodes (EDN Magazine) 7/27/2010
Real-Time Non-intrusive Debugging Framework (Design & Reuse) 7/23/2010
Give the People What They Want: HLS for RTL Verification (EE Times EDA Designline) 7/21/2010
Debug Will Get Your Attention, Sooner or Later (EE Times EDA Designline) 6/29/2010
Exploring Multicore Power Management with Modeling and Simulation (EE Times Embedded) 6/29/2010
Testing Your MEMS-Based Embedded Design for Hardware Faults (EE Times Embedded) 6/29/2010
Time Is Right for Clockless Design (EE Times EDA Designline) 6/29/2010
Using Standards-Based Tools to Scale Chip Designs to Next-Generation Geometries (EE Times Embedded) 6/29/2010
Verifying Your Configurable OCP Interfaces (EE Times Embedded) 6/29/2010
Path-Specific Derating to Reduce Timing Pessimism (EDN Magazine) 6/25/2010
How to Make Virtual Prototyping Better than Designing with Hardware: Part 2 - The Importance of Testability In Virtual Prototyping (EE Times Embedded) 6/23/2010
SystemVerilog-Based Generic Verification Methodology for IPs/ ASICs/ SOCs (Design & Reuse) 6/23/2010
Testing Embedded Data Buses and Analog Signals (EDN Magazine) 6/23/2010
Efficient C Programming and Its Effect On the Performance of Embedded Systems (EE Times Embedded) 6/22/2010
How to Make Virtual Prototyping Better than Designing with Hardware: Part 1 - Use Cases for Virtual Prototyping (EE Times Embedded) 6/22/2010
Is IP Integration the Real High-Level Design? (EDN Magazine) 6/21/2010
Achieving Verification Closure with Resource and Time Constraints (EE Times EDA Designline) 6/17/2010
Advancing Network Packet Management and Security Using Silicon Based Subsystem IP Solutions (Design & Reuse) 6/17/2010
Altering the SOC Design Flow (EDN Magazine) 6/17/2010
Creating Virtual Platforms Using the OCP-IP Modeling Kit (Design & Reuse) 6/17/2010
Low Power: A Chip and System-Design Primer (EDN Magazine) 6/17/2010
Power Analysis of Clock Gating at RTL (EE Times EDA Designline) 6/17/2010
Power-Grid Analysis on SOC Graphics Chip Design (EDN Magazine) 6/17/2010
Reducing Switching Power with Intelligent Clock Gating (EE Times Programmable Logic Designline) 6/17/2010
The Transformation of Silicon to System Design (Electronic Products Magazine) 6/1/2010
Transitioning from C/C++ to SystemC in High-Level Design (EE Times Embedded) 6/1/2010
Code Coverage Convergence In Configurable IP (Design & Reuse) 5/27/2010
Power Management for Optimal Power Design (EDN Magazine) 5/27/2010
Bringing MEMS Into the IC Design Flow (EE Times EDA Designline) 5/21/2010
Powering Down: Enabling a Power Regression Flow for SoC Design (EE Times Embedded) 5/13/2010
Using Unified Modeling Methods to Reduce Embedded Hardware/ Software Development (EE Times Embedded) 5/13/2010
DDGEN: An Automated Device Driver Generation Tool for Embedded Systems (Design & Reuse) 5/3/2010
Doing C-code Generation Better: From Graphical Code to Embedded Target (EE Times Embedded) 5/3/2010
Making Source Code Analysis Part of the Software Development Process (EE Times Embedded) 4/26/2010
Timing Closure On FPGAs (EE Times Programmable Logic Designline) 4/22/2010
Software Development Team Collaboration Across Disciplines Using UML/ SysML (EE Times Embedded) 4/20/2010
Embedded System Design with Open Source Software: Doing It Right (EE Times Embedded) 4/19/2010
Clearing the Hurdles of HLS Adoption (EE Times EDA Designline) 4/13/2010
Treat Programmable Hardware Design As a High-Level System Task (EE Times Embedded) 4/13/2010
Continuous-Time Equalizers Improve High-Speed Serial Links (EDN Magazine) 4/8/2010
Setting Up Hardware Verification Testbenches Using OVM Configuration Classes (EE Times Embedded) 4/5/2010
RTL Synthesis Can Accelerate the Entire Implementation Flow (EE Times EDA Designline) 3/31/2010
10 Questions to Ask When Choosing a Virtualization Solution (Electronic Engineering Times (EE Times)) 3/22/2010
Greening Multiprocessor Design (EE Times EDA Designline) 3/22/2010
Building Quality Assurance Into Your Hardware: EDA Is Not Enough! (EE Times EDA Designline) 3/17/2010
Power Delivery Network Design Requires Chip-package-system Co-Design Approach (EE Times EDA Designline) 3/15/2010
Verification of a USB 3.0 Device IP Core in Multi-Layer SystemC Verification Environment (Design & Reuse) 3/15/2010
ICE Debugging: The End of the Battleship Game (EE Times EDA Designline) 3/10/2010
Ensuring the Thermal Integrity of Your IC Package/ PC Board Design (EE Times Power Management Designline) 3/8/2010
Hardware Solutions to the Challenges of Multimedia IP Functional Verification (Design & Reuse) 2/25/2010
Software Architecture for IP verification in Operating System Environment (Design & Reuse) 2/25/2010
Dodging Amdahl's Law with Message Passing, FPGA-Based Parallel Processing (EE Times Programmable Logic Designline) 2/24/2010
Combating Congestion In High-performance, Low-cost SOCs (EDN Magazine) 2/23/2010
High-Level Synthesis, Verification and Language (EE Times EDA Designline) 2/22/2010
Tuning C/C++ Compilers for Optimal Parallel Performance In Multicore Applications: The Compiler Optimization Process - Part 2 (EE Times Embedded) 2/21/2010
Analog and Mixed-Signal Modeling Approaches (Design & Reuse) 2/18/2010
Tuning C/C++ Compilers for Optimal Parallel Performance In Multicore Applications - Part 1 (EE Times Embedded) 2/18/2010
Chip Synthesis: A New Approach to RTL Implementation (EE Times EDA Designline) 2/16/2010
Integrating Static Analysis with a Compiler and Database (Embedded Computing Design) 2/16/2010
Guidelines for Complex SOC Verification (EE Times EDA Designline) 2/15/2010
Re-Configurable Platform for Design, Verification and Implementation of SOCs (Design & Reuse) 2/11/2010
Debugging and Analysis with SystemVerilog Testbench (EDN Magazine) 2/4/2010
Tools Accurately Simulate Noise in Mixed-Signal ASICs (EDN Magazine) 2/4/2010
When Good Compilers Go Bad, or What You See Is Not What You Execute (EE Times Embedded) 2/3/2010
Automating Next-Generation Network-Design Tasks (EE Times Embedded) 2/2/2010
Improving Software Development and Verification Productivity Using IP-Based System Prototyping (Design & Reuse) 2/1/2010
A Recipe for Verification IP: The Role of Methodology (Design & Reuse) 1/26/2010
Embedded System Virtualization for Executable Specifications and Use Case Modeling (EE Times EDA Designline) 1/26/2010
Design for Diagnosis to Improve IC Yield (EE Times EDA Designline) 1/25/2010
Applying Virtual System Integration and Test to Validate Requirements and Verify Designs (EE Times EDA Designline) 1/22/2010
Early Verification Cuts Design Time and Cost In Algorithm-intensive Systems (EE Times EDA Designline) 1/22/2010
Methodology for Rapid Development of Loosely Timed and Approximately Timed TLM Peripherals (Design & Reuse) 1/21/2010
Automating the FPGA Design Debug Process (EE Times Embedded) 1/19/2010
Low-power LDPC Decoder Created Using High-Level Synthesis (EE Times EDA Designline) 1/13/2010
A Real Solution for Mixed Signal SOC Verification (EE Times EDA Designline) 1/7/2010
Under the Lid: Analog Test Is Suddenly the Critical Ingredient (EDN Magazine) 1/7/2010
Determine IC Transient Thermal Behavior to Prevent Overheating (EDN Magazine) 1/6/2010
Using OVM to Reuse Vital Verification Knowledge (EE Times EDA Designline) 1/5/2010
How Do You Qualify Netlist Reduction and Circuit Extraction? (EE Times EDA Designline) 1/4/2010

(back to top)

Tutorials, White Papers & Application Notes on EDA and EDA tools

0.3-mm Pitch Chip Scale Packages: Changes and Challenges (DfR Solutions)
2.5DIC, 3DIC, and 5.5DIC: Taking Integration Into the Third Dimension (Tech Design Forum)
9 Laws of Effective Systems Engineering (Vitech Corp.)
A 3D SOC Design for H.264 Application with On-Chip DRAM Stacking (Pennsylvania State University)
A Comparison of Two VHDL Memory Modeling Techniques (Free Model Foundry)
A Complete Design Solution for Structured ASICs (Magma Design Automation, Inc.)
A Cooperative Simulation Formal Methodology: Target Verification with Both Barrels (Test and Verification Solutions, Ltd. (TVS))
Accurate Quantitative Physics-of-Failure Approach to Integrated Circuit Reliability (DfR Solutions)
Achieving Low Power in 65-nm Cyclone III FPGAs (Altera Corp.)
Advanced Scoreboarding Techniques Using UVM (Test and Verification Solutions, Ltd. (TVS))
Advanced Virtual Platform Validation Methodology (JEDA Technologies, Inc.)
Already Scanned Today? (GOEPEL electronic GmbH)
An Introduction to IEEE 1666-2011, the New SystemC Standard (Accellera)
An Introduction to the Unified Coverage Interoperability Standard (Accellera)
An Introductory VHDL Tutorial (Green Mountain Computing Systems, Inc.)
Applying Agile Techniques to FPGA Development (Test and Verification Solutions, Ltd. (TVS))
Archipelago: An Open Source FPGA with Toolflow Support (University of California, Electrical Engineering)
ARM Cortex SoC Prototyping Platform for Industrial Applications (Aldec, Inc.)
Assertion Based Verification, ESL to Gate (JEDA Technologies, Inc.)
Assertion-Based Verification: Choosing the Right Solution (Atrenta, Inc.)
At 28nm, You Can't Afford a Free Lunch (Magma Design Automation, Inc.)
At-Speed SPI Flash and EEPROM Programming Using an FPGA and JTAG (ASSET InterTech, Inc.)
Automatic Formal Verification of Fused-­Multiply­-Add FPUs (IBM Corp.)
Automating Analog Verification in a Mixed-Mode Simulation (asicNorth)
Automating Sequential Clock Gating (Calypto Design Systems, Inc.)
Best Design Practices for High Capacity FPGA Devices (Aldec, Inc.)
Best Practices for Maximizing IP Reuse in SOC, IC and FPGA Design (IC Manage, Inc.)
Boundary Scan Tutorial (Corelis, Inc.)
Can We Train Our Designers to Avoid Bugs? (Test and Verification Solutions, Ltd. (TVS))
CDC Methodology for Fast-to-Slow Clocks (Real Intent, Inc.)
Challenges in Verification of Clock Domain Crossings (Real Intent, Inc.)
Challenges with Package-on-Package (PoP) (DfR Solutions)
Chill: A New Approach to Power Analysis (Envis Corp.)
Chip & Board Testability Assessment Checklist (ASSET InterTech, Inc.)
Clarifying Language, Methodology Confusion (Aldec, Inc.)
Clock and Reset Ubiquity: A CDC Verification Perspective (Real Intent, Inc.)
Clock Concurrent Optimization (Azuro, Inc.)
Clock Domain Crossing Demystified: The Second Generation Solution for CDC Verification (Real Intent, Inc.)
Coding Guidelines for Datapath Synthesis (Synopsys, Inc.)
Combining Impulse C with uClinux for MicroBlaze-based FPGAs (Impulse Accelerated Technologies, Inc.)
Combining Structural and Functional Verification Techniques to Improve Effective CDC Verification (Atrenta, Inc.)
CONNECT: Re-Examining Conventional Wisdom for Designing NoCs in the Context of FPGAs (Carnegie Mellon Electrical & Computer Engineering)
Continuous Integration for FPGA Design and Verification (Test and Verification Solutions, Ltd. (TVS))
CoRAM: An In-Fabric Memory Architecture for FPGA-based Computing (Carnegie Mellon Electrical & Computer Engineering)
Corporate Standardization of FPGA Design Flow (Aldec, Inc.)
Coverage Manager Methodology Accelerates Complex SOC Verification (Ingot Systems, Inc.)
C-To-CoRAM: Compiling Perfect Loop Nests to the Portable CoRAM Abstraction (Carnegie Mellon Electrical & Computer Engineering)
Debugging SCE-MI Co-Emulation in Riviera-PRO Simulation Environment (Aldec, Inc.)
Debugging Today's Complex Analog Designs Requires Much More than Waveform Analysis (Sandwork Design, Inc.)
Delivering Synthesizable Verification IP for Test Benches (Bluespec, Inc.)
Deploying Properties Assertions and Coverage (Aldec, Inc.)
Design for Testability: The Importance of Straightforward Solutions (GOEPEL electronic GmbH)
Design Management & IP Reuse Study (Gary Smith EDA)
Designer's Guide to Verilog (Doulos, Ltd.)
Design-for-Test Guidelines (Corelis, Inc.)
DO-254 Requirements Traceability (Aldec, Inc.)
Does ESL Really Need to Be That Hard to Use? (JEDA Technologies, Inc.)
Early Chip Sizing Carries High Financial and Technical Implications (Toshiba America Electronic Components, Inc. (TAEC))
EDA Grows Again: 2011 Complete Market Trends (Gary Smith EDA)
Effcient Symbolic Simulation via Dynamic Scheduling, Don't Caring, and Case Splitting (IBM Corp.)
Efficient Signal and Power Integrity Analysis Using Parallel Techniques (Sigrity, Inc.)
Electronic System-Level Development: Finding the Right Mix of Solutions for the Right Mix of Engineers (Byte Paradigm)
Electronic Systems Prototyping: Tools and Methodologies for Better Observability (Byte Paradigm)
Embedded Instrumentation: The Future of Advanced Design Validation, Test and Debug (ASSET InterTech, Inc.)
Embedded Systems Verification (Aldec, Inc.)
EMI Reduction and PCB Layout Techniques (TLSI, Inc.)
Emulation: Enabling It on Every Desktop (Bluespec, Inc.)
Enabling Assertion-Based Verification (Zocalo Tech, Inc.)
Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning (IBM Corp.)
Enhancing Verilog Designs with Embedded PSL (Aldec, Inc.)
Enhancing Verilog Designs with SVA (Aldec, Inc.)
Enhancing VHDL Designs with Embedded PSL (Aldec, Inc.)
Exploiting Constraints in Transformation-Based Verification (IBM Corp.)
Exploiting Suspected Redundancy without Proving It (IBM Corp.)
Four Reasons to Incorporate FPGA Technology Into Your Test Applications (National Instruments Corp.)
FPGA Design Practices Survey (GateRocket, Inc.)
FPGA-based Prototyping – Tackling Large Designs Earlier (Test and Verification Solutions, Ltd. (TVS))
Free Models: What Are They? How Are They Used? How Can They Be Free? (Free Model Foundry)
Getting Started with Requirements-Based Verification (Verilab, Ltd.)
Global Design Data Management Report 2010 (IC Manage, Inc.)
Global Design Data Management Report 2012 (IC Manage, Inc.)
Global Design Management Report 2009 (IC Manage, Inc.)
Global Design Management Report 2011 (IC Manage, Inc.)
Global Design Management Report 2012 (IC Manage, Inc.)
HDL Simulation and Mathematical Modeling Integration (Aldec, Inc.)
HES Simulation Acceleration (Aldec, Inc.)
HES-7 ASIC Prototyping (Aldec, Inc.)
High Performance Scalable Hardware Configuration Management (IC Manage, Inc.)
High-Level "Plug-and-Play" Specification, Modeling and Synthesis of Pipelined Architectures with Bluespec’s PAClib (Bluespec, Inc.)
High-Speed I/O Design Considerations in Low-Cost Packaging Applications (Toshiba America Electronic Components, Inc. (TAEC))
How to Minimize Energy Consumption While Maximizing ASIC and SOC Performance (Tensilica, Inc.)
I2C Functional Test with JTAG and FPGA IP (ASSET InterTech, Inc.)
IC Design Management Best Practices (IC Manage, Inc.)
Impact of Multiple-Voltage Domain Design Implementation on Large, Complex SoCs (Toshiba America Electronic Components, Inc. (TAEC))
Interoperable IP Delivery (Aldec, Inc.)
Introduction to Verilog (
Introduction to VHDL (
IP Reuse and Design Management in the SOC and IC Design Process (Gary Smith EDA)
IP Reuse: Design and Verification Report 2013 (IC Manage, Inc.)
IP Solutions for Synchronizing Signals that Cross Clock Domains (Synopsys, Inc.)
Is That an Elephant in Your Flow? (Duolog Technologies)
JTAG Guidelines for Board DFT: Part 1 (ASSET InterTech, Inc.)
JTAG Guidelines for Board DFT: Part 2 (ASSET InterTech, Inc.)
JTAG/ Boundary Scan: What Can It Do for You and What Do You Have to Do? (GOEPEL electronic GmbH)
Kelvin: A New Approach to Power Analysis (Envis Corp.)
Leveraging System Models for RTL Functional Verification Using Sequential Logic Equivalence Checking (Calypto Design Systems, Inc.)
Logical Hardware debuggers for FPGA-based Systems (BYU Configurable Computing Lab)
Magic of SDN in Networking (Calsoft Labs)
Making Floating-Point Arithmetic Work in Your RTL Design (Aldec, Inc.)
Meeting Growing Verification Demands (Aldec, Inc.)
Modeling OCP Interfaces in SystemC: Standards built on top of OSCI’s TLM-2 (OCP International Partnership (OCP-IP))
Multicore Programming Practices (MPP) Guide (Multicore Association)
Multimedia Application Specific Engine Design Using High Level Synthesis (Synfora, Inc.)
Navigating the System to RTL Continuum (Calypto Design Systems, Inc.)
NSCa and PSL: Why Native Assertion Is Iportant in SystemC? (JEDA Technologies, Inc.)
OCP TLM for Architectural Modeling (CoWare, Inc.)
OSCI TLM2.0 Standard Compliance: Why Bother? (JEDA Technologies, Inc.)
Power Management Poses a Critical Design Constraint in Consumer Applications (Toshiba America Electronic Components, Inc. (TAEC))
Power-Saving Clock-Gating Technique is an Inseparable Part of SoC Design (Toshiba America Electronic Components, Inc. (TAEC))
Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter Using SystemVerilog Assertions (Verilab, Ltd.)
Predictable Verification Productivity (Test and Verification Solutions, Ltd. (TVS))
Prototype and Evaluation of the CoRAM Memory Architecture for FPGA-based Computing (Carnegie Mellon Electrical & Computer Engineering)
Quantitatively Analyzing the Performance of Integrated Circuits and Their Reliability (DfR Solutions)
Reducing AMBA-based SoC Design Time by More Than 50% Using coreAssembler (Synopsys, Inc.)
Reducing the Cost of FPGA/ASIC Verification with MATLAB and Simulink (Test and Verification Solutions, Ltd. (TVS))
Requirements-Driven Verification for Compliance (Test and Verification Solutions, Ltd. (TVS))
Scalable Automated Verification via Expert-System Guided Transformations (IBM Corp.)
Scalable Compositional Minimization via Static Analysis (IBM Corp.)
Scalable Sequential Equivalence Checking Across Arbitrary Design Transformations (IBM Corp.)
Sequential Equivalence Checking: A New Approach to Functional Verification of Datapath and Control Logic Changes (Calypto Design Systems, Inc.)
Shorten and Simplify SoC Verification using a Generic eVC (Verilab, Ltd.)
Si2 Power Aware Design Flows (Silicon Integration Initiative, Inc. (Si2))
Si2 Power Reduction Stimulus and Low Power Design Techniques (Silicon Integration Initiative, Inc. (Si2))
Silicon Design Chain Extends Low Power Design Collaboration (Cadence Design Systems, Inc.)
Single-chip Heterogeneous Computing: Does the Future include Custom Logic, FPGAs, and GPUs? (Carnegie Mellon Electrical & Computer Engineering)
Solutions for SPI Protocol Testing and Debugging in Embedded System (Byte Paradigm)
Successfully Designing FPGA-Based Systems (Cadence Design Systems, Inc.)
Synthesizable Models Enable Early Emulation for Complex IP (Bluespec, Inc.)
System Level Design and Verification Using a Synchronous Language (Formal Sciences, Inc.)
System Level Design: SystemC Using Transaction Level Modeling (Aldec, Inc.)
SystemC Training Course (Forte Design Systems, Inc.)
SystemC Tutorial (ASIC World)
SystemC: An Introduction for Beginners (
SystemC-based UVM Verification Infrastructure (Test and Verification Solutions, Ltd. (TVS))
SystemVerilog Implicit Port Connections: Simulation and Synthesis (Sunburst Design, Inc.)
SystemVerilog Scheduling Semantics (Test and Verification Solutions, Ltd. (TVS))
SystemVerilog Tutorial (ASIC World)
SystemVerilog Tutortial (
Testing DDR Memory with Bondry Scan/JTAG (ASSET InterTech, Inc.)
The Challenges Are Changing for System Design (Altera Corp.)
The DFM Pandemic: How Many Chips Have to Die? (Pyxis Technology, Inc.)
The Low-Carb VHDL Tutorial (University of Central Florida, EECS)
The Myth of SystemVerilog Interoperability (Verilab, Ltd.)
The Open Verification Methodology (OVM), (OVM World)
The Power of RTL Clock Gating (Calypto Design Systems, Inc.)
Those Pesky Interfaces… (Aldec, Inc.)
TLM-2.0 in Action: An Example-based Approach to Transaction-Level Modeling and Model Interoperability (Open SystemC Initiative (OSCI))
Tool Assessment and Qualification with the Aldec DO-254 Compliance Tool Set (Aldec, Inc.)
Unified TLM 2.0 Coverage Measurement (JEDA Technologies, Inc.)
Unifying Bug Tracking with Design-Data Management (IC Manage, Inc.)
Using Boundary Scan to Link Design and Manufacturing Test (ASSET InterTech, Inc.)
Using FPGA Prototyping Board as an SoC Verification and Integration Platform (Aldec, Inc.)
Using FPGA-Based Simulation Acceleration In a Typical ASIC Design Flow (Aldec, Inc.)
Using IC Manage GDP for Collaborative Custom IC (Virtuoso) and Digital SOC Design (IC Manage, Inc.)
Using Impulse C with BlueCat Linux 5.4.2 on MicroBlaze via FSL (Impulse Accelerated Technologies, Inc.)
Using Plots for HDL Debugging as a Powerful Alternative to Traditional Waveforms (Aldec, Inc.)
Using Program Specialization to Speed SystemC Fixed-Point Simulation (Formal Sciences, Inc.)
Using SystemVerilog Assertions for Functional Coverage (Verilab, Ltd.)
Using SystemVerilog Assertions in Gate-Level Verification Environments (Verilab, Ltd.)
Utilizing Clock-Gating Efficiency to Reduce Power in RTL Designs (Calypto Design Systems, Inc.)
UVM Register Modelling: Advanced Topics (Test and Verification Solutions, Ltd. (TVS))
UVM Status and Plans (Test and Verification Solutions, Ltd. (TVS))
UVM: Ready, Set, Deploy! (Accellera)
Variation Analysis and Design for Custom ICs (Gary Smith EDA)
Variation-Aware Custom IC Design Report 2011 (Solido Design Automation, Inc.)
VERA Verification Tutorial (ASIC World)
Verification and Automation Improvement Using IP-XACT (Accellera)
Verification IP – Trends and Technology for FPGA and ASIC Design Verification (Test and Verification Solutions, Ltd. (TVS))
Verification of Ethernet Designs with SCE-MI based Aldec Emulator (Aldec, Inc.)
Verification without Testbenches (Calypto Design Systems, Inc.)
Verilog HDL Quick Reference Guide (Sutherland HDL, Inc.)
Verilog Tutorial (University of Maryland (ECE))
Verilog Tutorial (Yankee Bush Software)
VHDL PaceMaker Interactive Tutorial (Doulos, Ltd.)
VHDL Test Bench Tutorial (University of Pennsylvania, ESE)
VHDL Tutorial (University of Pennsylvania, ESE)
VHDL Tutorial (ASIC World)
VHDL Tutorial (University of Erlangen-Nürnberg)
VHDL Tutorial (Yankee Bush Software)
VHDL Verification Course (Stefan Doll)
Virtual Modeling with Aldec and Imperas (Aldec, Inc.)
Virtual Platforms for Software Development (CoWare, Inc.)
We Haven’t Survived 65nm: We’re Just in the Eye of the Storm! (Pyxis Technology, Inc.)
What Is Assertion-Based Verification? (Tech Design Forum)
What Is Emulation? (Tech Design Forum)
What is FPGA prototyping? (Tech Design Forum)
What Is System Virtual Prototyping? (Tech Design Forum)
What is SystemC? (Tech Design Forum)
What Is Transaction-Level Modeling? (Tech Design Forum)
What Is Verification IP? (Tech Design Forum)
What Is VHDL? (Tech Design Forum)
What Your SOC Designer Might Not Tell You About Power Management (Altera Corp.)
Who's Managing Your Power Management? (JVD, Inc.)

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