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 Category: Intellectual Property: Tuesday, June 18, 2013
 Intellectual Property

OCP-IP Newsletter
April 2013

SOCcentral.com maintains a database of several hundred IP suppliers that include links to their news announcement, articles that have been published online, and whitepapers available online.

Simon Butler
MethodICs

The IP Distribution Challenge

What comes to mind when you hear the term IP Distribution? How do people like ARM and MIPS get their cores into people's hands? Pricing, contracts and legal issues? Maybe third-party websites like Chip Estimate and Design & Reuse? Yes, they are all factors in how independently developed IP gets distributed to users. But as the commercial IP industry matures, these things are getting much more efficient and well-oiled. ... read more.


Nikos Zervas
CAST

Leapfrogging the Competition Through Smart IP Selection

The adoption of a reliable design reuse methodology, proliferation of high-quality IP products, and shake-out of the most un-trustworthy IP vendors creates a situation offering a huge potential advantage to system integrators and product designers. Instead of choosing the same big-vendor, star IP, smarter firms will seek out and commit to what might be technically superior IP products from smaller vendors/ partners who will offer deeper and broader service and support. ... read more.

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Recent SOCcentral news articles on Intellectual Property (last 6 weeks)

Atmel Announces New ARM Cortex-M0+ Microcontroller Family (6/17/2013)
Imagination Signs License Agreement with Cavium for MIPSr5 Architecture (6/17/2013)
Intellitech Supports Silicon Instruments Through the New IEEE 1149.1-2013 JTAG Standard (6/17/2013)
Microsemi Announces System Builder Design Tool for ARM-based SmartFusion2 SoC FPGA Designs (6/17/2013)
Arasan Chip Systems introduces USB 3.0 SSIC Bridge IP (6/12/2013)
Carbon Expands Reach of Model-Swap Technology (6/12/2013)
Huanor Adopts Cypress's EZ-USB FX3 Peripheral Controller for USB 3.0 Industrial Camera Development Kit (6/12/2013)
Synopsys Announces Design Kit Optimized for All SoC Processor Cores (6/12/2013)
Rambus and SK Hynix Sign Patent-License Agreement (6/11/2013)
Altera Licenses Arteris FlexNoC Interconnect Fabric IP for ARM-based Processor Systems (6/10/2013)
Analog Bits' Secure Clock IP Core Reduces Cost, Lowers Power and Increases Security (6/10/2013)
ARM and GlobalFoundries to Optimize Next-Generation ARM Mobile Processors for 28-nm SLP Process Technology (6/10/2013)
ARM Announces AMBA 5 CHI Specification (6/10/2013)
BaySand Selects Sibridge Technologies' Design and Verification IP for Mask-Configurable Standard-Cell Platform (6/10/2013)
Blue Pearl Software Suite Now Available for Purchase Through the Embedded Software Store (6/10/2013)
eMemory and UMC Expand Non-volatile Memory Cooperation to Advanced 28-nm Process (6/10/2013)
Energy Mirco's Cortex-M4 Wonder Gecko MCU Features New VarioTAP Emulation Test (6/10/2013)
eSilicon and GlobalFoundries Partner with QuickLogic to Deliver the ArcticLink III Family of Display Bridge Solutions (6/10/2013)
Jasper and Duolog Partner to Combine SOC Integration with Formal Verification (6/10/2013)
Low-Power BA21 Processor Core Brings 32-bit Benefits to Embedded Microcontroller Applications (6/10/2013)
Mentor Graphics Questa and Veloce Verification Platforms Add Cache Coherency and Interconnect Performance for ARM AMBA 5 CHI and AMBA 4 ACE Designs (6/10/2013)
Microchip Technology's SST Subsidiary and Novocell Semiconductor Announce Acquisition of Novocell by SST (6/10/2013)
Microsemi Adopts Cortus Processor Core for New Mixed-Signal SOC Platform for Industrial Applications (6/10/2013)
Moortec Semiconductor Announces its Embedded Voltage Monitor IP on 28nm (6/10/2013)
PLDA and IP-Maker Enable High-Performance Storage Devices with Integrated PCIe 3.0 Controller with NVM Express IP Core (6/10/2013)
Ricoh Licenses Vayavya's DDGen Tool for Automated Device-Driver Generation (6/10/2013)
SilabTech's 28-nm High-Speed PHYs Delivered Ahead of Schedule with Mentor Graphics Tool Flow (6/10/2013)
Target Compiler Technologies Expands Architectural Exploration into IP Subsystem Design (6/10/2013)
True Circuits Introduces New DDR 4/3 PHY (6/10/2013)
ARM and Carbon Expand Partnership to Include Cortex-A57 and Cortex-A53 Processors, CoreLink System IP (6/3/2013)
Digital Core Design Announces D68HC11, HC11 Legacy with All Peripherals On Board (6/3/2013)
HiSilicon Using Arteris FlexNoC Interconnect Fabric IP in Multiple Product Lines (6/3/2013)
Samplify's APAX Technology Cuts Memory Power Consumption by 59% During Video Playback on Mobile Devices (6/3/2013)
Si2 Co-Sponsors Low-Power Standardization Futures Meeting at DAC (5/30/2013)
ARM Announces Power-Optimized Dual-Core ARM Cortex-A15 Hard Macro (5/29/2013)
Synopsys Introduces Starter Kit for DesignWare ARC EM Processors (5/29/2013)
Kilopass and UMC Align for Advanced 28-nm IP (5/28/2013)
RDA Microelectronics Boosts Mobile Phone Performance with Arteris FlexNoC Interconnect IP (5/28/2013)
Dolphin Integration Announces New Generation of Ultra-dense Standard-Cell Library for GSMC 0.180-nm uLL eFlash process (5/27/2013)
LG Electronics Becomes Lead Partner for ARM Cortex-A50 CPUs and Next-Generation Mali GPUs (5/23/2013)
MOSCAD Design & Automation Achieves New Milestone in Fully Integrated Silicon Oscillators (5/23/2013)
Nvidia Adopts Arrow Devices' UniPro CheckMate Verification Solution (5/23/2013)
Imperas Delivers Next-Generation Embedded-Software Development Suite Based on ToolMorphing Technology (5/22/2013)
50th DAC Announces First-Ever Training Day to Keep EDA Users Updated on Latest Design Techniques (5/21/2013)
Altera Stratix V GX FPGAs Achieve PCIe Gen3 Compliance and Listing on PCI-SIG Integrators List (5/21/2013)
Avery Design Systems Announces eMMC and SD Verification IP Solutions (5/21/2013)
EnSilica Partners with Cross Border Technologies to Accelerate Sales Growth in key European and Asian Markets (5/21/2013)
Imec and GlobalFoundries Collaborate to Advance High-Density Memory Technology (5/21/2013)
Microsemi Shipping Production-qualified SmartFusion2 SoC FPGAs and Full-featured Development Kit (5/21/2013)
Praesum Communications Introduces Serial RapidIO End-Point Core for AMBA 4 AXI4 (5/21/2013)
Fourth Multicore Challenge Now Open for Registration (5/20/2013)
QuickLogic Parallel Camera Interface for TI Sitara AM335x ARM Cortex-A8 Processors Supports Android Jelly Bean 4.1.2 OS (5/20/2013)
sureCore Receives SMART Award to Prototype Its Low-Power SRAM Technology (5/20/2013)
Synopsys DesignWare IP for PCI Express 3.0 Passes First PCI-SIG PCIe 3.0 Compliance Workshop (5/20/2013)
Test and Verification Solutions Expands Library of Verification IP (5/20/2013)
Xilinx Achieves PCI Express Compliance Across Its All Programmable 28-nm Devices (5/20/2013)
Ultra-Low Latency H.264 Video Encoding Now Available from CAST (5/16/2013)
New Power ISA 2.07 Now Available from Power.org (5/15/2013)
Altera to Acquire Enpirion (5/14/2013)
Chip Memory Technology Emerges from Stealth Mode to Reveal New Embedded NV Memory Solution (5/14/2013)
Elecard Releases New Version of Elecard ARM Codec SDK (5/14/2013)
TI Delivers ZigBee SOC with an ARM Cortex-M3 MCU (5/14/2013)
Energy-Efficient EFM32 Wonder Gecko with ARM Cortex-M4 and FPU Now Available (5/13/2013)
HiSilicon Technologies Tapes Out 50+ Million Instance ARM Processor-based SOC Using Synopsys IC Compiler (5/13/2013)
Management Day at DAC to Discuss the Trade-Offs Involved in Modern SOC Design (5/13/2013)
Si2 Celebrates Its 25th Anniversary with Complimentary Lunch and Evening Reception During DAC (5/13/2013)
UltraSoC Delivers Universal Debug IP to PMC-Sierra (5/13/2013)
eMemory Announces NeoFuse Anti-Fuse eNVM Technology (5/8/2013)
Broadcom Introduces Low-Power Processor SOC for Switch Control-Plane Applications (5/7/2013)
Broadcom Unveils Highly Integrated Processor SOC for 5G WiFi Enterprise Access Points (5/7/2013)
Cadence to Acquire Evatronix's IP Business (5/7/2013)
S3 Group Licenses Custom ADC and DAC Solutions to Avalent Technologies (5/7/2013)
STMicroelectronics and Quantenna Enter Strategic Licensing Agreement (5/7/2013)
Tanner EDA Joins ARM Connected Community (5/7/2013)

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Magazine & Journal articles on Intellectual Property

A Generic DDR Behavioural Model (Design & Reuse) 5/22/2013
Leveraging PCIe SSD Performance with a Full Hardware NVMe (Chip Estimate Corp.) 5/21/2013
Building an RTL Sign-off Flow (Tech Design Forum) 5/14/2013
Customizing SRAM Content to Obtain Truly Differentiated Products (Chip Estimate Corp.) 5/14/2013
How Small Vendors Compete on Analog IC Market (EE Times Test & Measurement Designline) 4/29/2013
The Use of FinFETs in IP Design (Chip Estimate Corp.) 4/23/2013
Using Audio Codec IP as the Digital Audio Hub in Mobile Multimedia Systems (EDN Magazine) 4/23/2013
FPGAs Offer Cost-Effective, Flexible Solutions for Remote Radio Heads (EE Times Programmable Logic Designline) 4/18/2013
Complex Standards Demand New Approaches to IP Quality (Chip Estimate Corp.) 4/16/2013
Stitch and Ship No Longer Viable (EE Times EDA Designline) 4/15/2013
SOC FPGAs Combine Performance and Flexibility (EDN Magazine) 4/10/2013
SSM Policy-Driven System Management Updates SOC Architecture to Meet Today's Operation Complexities (Chip Estimate Corp.) 4/9/2013
Building Your UVM Verification Environment for Cache-Coherent Interconnects (Design & Reuse) 4/4/2013
Extreme Code Density: Energy Savings and Methods (Chip Estimate Corp.) 4/2/2013
Dynamic Partitioning Speeds Memory Characterization (EE Times Memory Designline) 3/25/2013
The Challenges of Using Open-Market IP in ASIC Designs (Chip Estimate Corp.) 3/19/2013
Hardware (and Software) Implications of Endianness in SOC Design (Embedded.com) 3/17/2013
Tensilica Acquisition to Accelerate Cadence Core Strategy (Electronic Engineering Times (EE Times)) 3/13/2013
The Coming Impact of Mobile PCI Express (M-PCIe) on SOCs and Devices (Chip Estimate Corp.) 3/12/2013
Virtual Prototyping Methodology to Boot Linux on the ARM Cortex A15 (EE Times EDA Designline) 3/11/2013
Virtual Prototyping Methodology to Boot Linux on the ARM Cortex A15 (EE Times EDA Designline) 3/11/2013
Analyzing the Options in High-Bandwidth System Interconnect (Altera Corp.) 3/8/2013
State of RTL-based Design: Is It Time to Move Beyond? (Design & Reuse) 2/25/2013
Using 3rd-Party IP in ASIC/SOC Design (EE Times EDA Designline) 2/25/2013
Voltage-Controlled MRAM: Status, Challenges and Prospects (EE Times Memory Designline) 2/25/2013
Designing Low-Power Video Image Stabilization IP for FPGAs (EE Times Militray & Aerospace Highlights) 2/19/2013
Accelerated VIP Solves Firmware and Driver Integration and Validation Trade-Offs (Tech Design Forum) 1/31/2013
Extreme Code Density: Energy Savings and Methods (Chip Estimate Corp.) 1/29/2013
Verification IP: The Questions You Should Ask (Tech Design Forum) 1/24/2013
Understanding SATA FIS-Based Switching (Chip Estimate Corp.) 1/22/2013
Get More out of System Architectures (Tech Design Forum) 1/18/2013
Smart Power Hook-Up Methodology for Memories on SOCs (EDN Magazine) 1/16/2013
Why USB 3.0 Will Drive SOC Verification in 2013 (Chip Estimate Corp.) 1/15/2013
Integrating Large-Capacity Memory in Advanced-Node SOCs (EE Times Memory Designline) 1/14/2013
Customizing SRAM Content to Obtain Truly Differentiated Products (Chip Estimate Corp.) 12/25/2012
Seismic Shifts Await EDA in a More-than-Moore World (Electronic Design Magazine) 12/20/2012
Smashing Through the Mobile Device Memory Bottleneck (Chip Estimate Corp.) 12/11/2012
High-Performance Logic Libraries for Core Hardening (Chip Estimate Corp.) 12/4/2012
Debunking Myths About Analog IP at 20nm (EE Times Planet Analog) 12/3/2012
Design Reuse without Verification Reuse Is Useless (EE Times EDA Designline) 11/26/2012
Alternative NVM Technologies Require New Test Approaches-Part 2 (EE Times Memory Designline) 11/20/2012
Selecting Embedded SRAM to Meet LowiVoltage Requirements (Chip Estimate Corp.) 11/20/2012
Alternative NVM Technologies Require New Test Approaches-Part 1 (EE Times Memory Designline) 11/13/2012
ARM vs. Incumbent Microprocessor Architectures (EDN Magazine, ) 11/13/2012
Optimizing Memory Design (EE Times Memory Designline) 11/13/2012
What's the Difference Between de Jure and de Facto Standards? (Electronic Design Magazine) 11/13/2012
Protecting Display Data in TrustZone-Enabled SoCs with the Evatronix Panta Family of Display Processors (Design & Reuse) 11/8/2012
ARM-Based Android Hardware/Software Design Using Virtual Prototypes-Part 2: Building a Sensor Subsystem (EE Times Embedded) 11/7/2012
Implementing Digital Processing for Automotive Radar Using SOC FPGAs (EE Times Programmable Logic Designline) 11/6/2012
SSM Policy Driven System Management Updates SoC Architecture to Meet today's Operation Complexities (Chip Estimate Corp.) 11/6/2012
Right-Sizing Your Processor Selection (EDN Magazine) 11/5/2012
ARM-Based Android Hardware/Software Design Using Virtual Prototypes-Part 1: Why Virtualize? (EE Times Embedded) 10/27/2012
RTL Analysis for Complex FPGA Designs Using a Grey Cell Methodology (EE Times Programmable Logic Designline) 10/26/2012
Understanding 28-nm SOC Design with ARM-Based Cores (Electronic Design Magazine) 10/19/2012
One Processor to Rule Them All? (EDN Magazine) 10/18/2012
Processor Architectures: the Sweet-Spot Spectrum (EDN Magazine) 10/18/2012
Marketing and Technology Collide in Competitive Chip Design (Electronic Design Magazine) 10/11/2012
M-PHY Benefits and Challenges (Chip Estimate Corp.) 10/9/2012
Multicore ARM SOCs Face Cache Coherency Dilemma (Chip Estimate Corp.) 10/2/2012
Addressing Memory Performance for 100G Ethernet Networking (Chip Estimate Corp.) 9/18/2012
Designing a NVMe-Compliant PCIe SSD (Chip Estimate Corp.) 9/4/2012
6 Reasons You Should Customize Your DSP Cores (Chip Estimate Corp.) 9/1/2012
Growing Audio Requirements in SOCs (EE Times Audio Designline) 8/23/2012
Proposal for a Dynamically Reconfigurable Processor Architecture with Multi-Accelerator (Design & Reuse) 8/20/2012
Move to Broader Coverage in SOC Verification Metrics (Electronic Design Magazine) 8/16/2012
Growing Audio Requirements in SOCs (EDN Magazine) 8/7/2012
How Flash and DRAM Growth Trends are Reshaping the Memory Industry (Chip Estimate Corp.) 8/7/2012
Breaking Through the Embedded Memory Bottleneck-Part 1 (EE Times Memory Designline) 7/30/2012
ASIC Implementation of a Speech Detector IP-Core for Real-Time Speaker Verification (Design & Reuse) 7/24/2012
Integrate More Analog into Your Digital Designs (Electronic Design Magazine) 7/24/2012
Using Code-Coverage Analysis to Verify 2D Graphic Engines in Automotive Apps (EE Times Automotive Designline) 7/20/2012
Design of a 8051 Microcontroller in FPGA with Reconfigurable Instruction Set (Design & Reuse) 7/19/2012
The Fundamentals of Integrating USB 3.0 IP on an SoC (Electronic Design Magazine) 7/18/2012
Understanding FPGA Processor Interconnects (Electronic Design Magazine) 7/17/2012
Embedded Success: It's About More than Just the Core (Electronic Design Magazine) 7/11/2012
Integrating IDE and RTOS for ARM-based Development (EE Times Industrial Control Designline) 7/11/2012
Enabling Error Resilience Throughout the Embedded System (EE Times Programmable Logic Designline) 7/10/2012
Understanding Virtual Sensors: From Sensor Fusion to Context-Aware Applications (Electronic Design Magazine) 7/10/2012
Anti-Fuse Memory Provides Robust, Secure NVM Option (EE Times Memory Designline) 7/5/2012
How-to Guide for On-Chip Memory (Electronics Weekly) 6/26/2012
Pseudo-Hardening in SOC Design (EDN Magazine) 5/25/2012
How to Use the CORDIC Algorithm in Your FPGA Design (EE Times Programmable Logic Designline) 5/12/2012
Lessons in Developing and Deploying OVM-Compliant VIP (Design & Reuse) 5/3/2012
ADC Performance: What's Jitter Got to Do with It? (Electronic Design Magazine) 4/25/2012
Optimizing Performance, Power, and Area in SOC Designs Using MIPS Multi-Threaded Processors (EE Times EDA Designline) 4/4/2012
Unified C-Programmable ASIP Architecture for Multi-Standard Viterbi, Turbo and LDPC Decoding (Design & Reuse) 3/28/2012
Ensuring Successful Third-Party Intellectual Property Integration (EE Times EDA Designline) 3/26/2012
Fundamentals of Floor Planning a Complex SOC (Electronic Design Magazine) 3/21/2012
Integrating Audio Codecs in Next-Generation SOCs for Smartphones and Tablets (EE Times Audio Designline) 3/20/2012
Software-Generated BCH As a Way to Solve Challenges of Providing Multiple Configuration IP (Design & Reuse) 3/6/2012
Mixed-Signal IP Design Challenges in 28nm and Beyond (Design & Reuse) 3/1/2012
Formal Techniques for Protocol Verification: A Case Study on Verifying the ARM ACE Protocol (Electronic Design Magazine) 1/11/2012
How Formal MDV Can Eliminate IP Integration Uncertainty (EE Times EDA Designline) 1/9/2012
Functional Coverage Analysis for IP Cores and an Approach to Scale Down Overall Simulation Time (Design & Reuse) 1/3/2012
Automating Design Rule Waivers in SOC IP Reuse (Electronic Design Magazine) 12/27/2011
Prototyping Mesh-of-Tree NOC-Based MPSOC on Mesh-of-Tree FPGA Devices (Design & Reuse) 11/23/2011
Overcoming 40G/100G SerDes Design And Implementation Challenges (EE Times EDA Designline) 11/2/2011
Open Standards Are Better than Open Source (Electronics Weekly) 10/26/2011
The Basics of Low-Power Programming on the Cortex-M0 (EE Times Embedded) 10/25/2011
Big.LITTLE Processing with ARM Cortex-A15 and Cortex-A7 (EE Times MCU Designline) 10/24/2011
Implementing High-Speed USB Functionality with FPGA- and ASIC-Based Designs (EE Times Programmable Logic Designline) 10/18/2011
Basics of Porting C-code to and between ARM CPUs: ARM7TDMI and Cortex-M0 (EE Times Embedded) 10/17/2011
Argument for Anti-Fuse Non-Volatile Memory in 28-nm High-K Metal Gate (EE Times Memory Designline) 10/15/2011
25-28Gbps SerDes Design and Implementation Challenges (Chip Estimate Corp.) 10/4/2011
A Practical Approach to IP Quality Inspection (EE Times EDA Designline) 9/26/2011
Managing IP Quality in the SOC Era Requires a Purpose-Built DM Approach (Electronic Engineering Times (EE Times)) 9/19/2011
Breaking the Language Barriers: Using Coverage Driven Verification to Improve the Quality of IP (Design & Reuse) 9/1/2011
Many-Core: Finding the Best Multi-Processing Tile (EE Times EDA Designline) 8/29/2011
Cryptography in Software or Hardware: It Depends on the Need (EE Times Embedded) 8/28/2011
Basics of Core-Based FPGA Design-Part 4: Implementing a Design (EE Times Embedded) 8/22/2011
Basics of Core-Based FPGA Design-Part 2: System Design Considerations (EE Times Embedded) 8/21/2011
Basics of Core-Based FPGA Design-Part 3: Picking the Right Core Options (EE Times Embedded) 8/21/2011
Basics of Core-Based FPGA Design-Part 1: Core Types & Trade-Offs (EE Times Embedded) 8/17/2011
Interconnect Solutions for 40G/100G Systems (Design & Reuse) 8/4/2011
Designing with Core-Based High-density FPGAs (EE Times Embedded) 7/27/2011
SPVR: An IP Core for Real-Time Speaker Verification (Design & Reuse) 7/21/2011
Tracking PLL Design Through the Decades-Part 1 (EDN Magazine) 7/14/2011
Tracking PLL Design Through the Decades-Part 2 (EDN Magazine) 7/14/2011
Creating an SOC Virtual Platform for Embedded Software Development (Electronic Design Magazine) 6/28/2011
Application Driven Network on Chip Architecture Exploration & Refinement for a Complex SOC (Design & Reuse) 6/20/2011
Breaking the Language Barriers: Using Coverage Driven Verification to Improve the Quality of IP (Design & Reuse) 6/20/2011
Moore's Law; the Bifurcation of the Semiconductor Industry and 3-D integration (Electronic Engineering Times (EE Times)) 6/16/2011
A Case for Custom Power Management ASICs (Design & Reuse) 6/8/2011
Power Optimization in Image Superscalar IP (Design & Reuse) 5/26/2011
Improving Today's Multimedia Products with 3rd-Party Audio IP Solutions (EE Times Audio Designline) 5/25/2011
Advanced Power Management in Embedded Memory Subsystems (Design & Reuse) 5/19/2011
Plan Strategies for Adopting Model-Based Design for Embedded Applications: Part 4 - Implementation, Verification and Validation (EE Times Automotive Designline) 4/21/2011
Systematic Approach to Verification of a Mixed-Signal IP: HSIC PHY Case Study (Design & Reuse) 4/21/2011
Minimal Effort Chip Design Using IP (Design & Reuse) 4/14/2011
ARM vs. Intel: A Successful Stratagem for RISC or Grist for CISC's Tricks? (EDN Magazine) 4/7/2011
Get the Lowdown on Accellera's VIP and UVM (Chip Design Magazine) 4/1/2011
In IP We Trust? (Chip Design Magazine) 4/1/2011
Automating Design Rule Waivers in SOC IP Reuse (Design & Reuse) 3/31/2011
Complete NAND Flash Solution: Logic, PHY and File System Software (Design & Reuse) 3/31/2011
Vertically Integrated MIPI Solutions (Design & Reuse) 3/24/2011
Analog IP for Multimedia SOCs: An Eye on a World of Essential Analog Features (EE Times Planet Analog) 3/22/2011
Verification of USB 3.0 Device IP Core in Multi-Layer SystemC Verification Environment (Design & Reuse) 3/17/2011
Hardware Co-Verification Using VMM HAL-SCEMI (Design & Reuse) 3/10/2011
Planning Reset Strategy: Flow and Functionality in OVC (EE Times EDA Designline) 3/9/2011
CPUs in FPGAs: Many Faces to a Trend (EDN Magazine) 3/3/2011
Adding Encryption to Disk Drives Is Made Easy Using an IP Core (EE Times Programmable Logic Designline) 3/2/2011
Virtual Channels Hardware Support in Switches in Relation to NoC Costs, Functions and Features (Design & Reuse) 2/21/2011
Hardware Solutions to the Challenges of Multimedia IP Functional Verification (Design & Reuse) 2/16/2011
Importance of Dynamic Programming for Achieving Hard Breakdown in Anti-Fuse Technology (Design & Reuse) 2/3/2011
How Are Competitors Differentiating Cortex-M3 based MCUs? (New Electronics Magazine) 1/10/2011
Choosing an Effective Embedded SOC ASIC Design Strategy (EE Times Embedded) 12/13/2010
A Memory Subsystem Model for Evaluating Network-on-Chip Performance (Design & Reuse) 12/2/2010
A Methodology for Describing Analog/ Mixed-Signal Blocks as IP (Design & Reuse) 11/25/2010
The Expanding Floating-Point Performance Gap Between FPGAs and Microprocessors (HPCwire) 11/22/2010
Innovation Led Business Models for IP's In Product Engineering (Design & Reuse) 11/18/2010
Trace-Based Approach for Unit-Level Debug and Verification of C/C++ IP Models (Design & Reuse) 11/18/2010
New IC Verification Techniques for Analog Content (EE Times EDA Designline) 11/17/2010
SOC DFT Verification With Static Analysis and Formal Methods (Test & Measurement World) 11/17/2010
eFPGA Creator GUI Tools Suite: A Complete Hardware and Software Infrastructure for Creating Customizable eFPGA IP Blocks (Design & Reuse) 11/4/2010
Will IP Use Increase In Forthcoming SOC Design? (Electronic Engineering Times (EE Times)) 11/4/2010
A Developer's Insight Into ARM Cortex-M Debugging (EE Times Embedded) 11/3/2010
Application Specific IP: Ensuring Semiconductor IP Quality (Design & Reuse) 10/28/2010
DSP Options to Accelerate Your DSP+FPGA Design (EE Times Signal Processing DesignLine) 10/25/2010
HW/SW Interface Generation Flow Based on Abstract Models of System Applications and Hardware Architectures (Design & Reuse) 10/25/2010
Use of an IP-core Development Process to Achieve Time-to-Market and Quality Assurance In a Multi-Project Environment (Design & Reuse) 10/25/2010
Design Environment for the Support of Configurable Network Interfaces in NoC-based Platforms (Design & Reuse) 10/21/2010
EDA's Next Step: System-Level Design Automation (Electronic Design Magazine) 10/20/2010
How to Choose Great IP (Design & Reuse) 10/6/2010
A Primer for Successful Integration of Complex Hard IP In Physical Design (EDN Magazine) 9/13/2010
IP Integration: Is It the Real System-Level Design? (EDN Magazine) 8/16/2010
Reduce Embedded SOC Design Cost and Optimize IP Integration (EE Times Embedded) 8/16/2010
Customized FPGA board for ASIC Prototyping: A Novel Approach with Pre-designed Blocks and Modular FPGA (Design & Reuse) 7/29/2010
IP Re-Engineering and Design Methodology (Design & Reuse) 7/29/2010
Verifying Your Configurable OCP Interfaces (EE Times Embedded) 6/29/2010
Is IP Integration the Real High-Level Design? (EDN Magazine) 6/21/2010
Advancing Network Packet Management and Security Using Silicon Based Subsystem IP Solutions (Design & Reuse) 6/17/2010
Altering the SOC Design Flow (EDN Magazine) 6/17/2010
Creating Virtual Platforms Using the OCP-IP Modeling Kit (Design & Reuse) 6/17/2010
Power Optimization In Image Superscalar IP (Design & Reuse) 6/17/2010
Power-Grid Analysis on SOC Graphics Chip Design (EDN Magazine) 6/17/2010
Repeatable Results with Design Preservation (EE Times Programmable Logic Designline) 6/17/2010
The Transformation of Silicon to System Design (Electronic Products Magazine) 6/1/2010
Code Coverage Convergence In Configurable IP (Design & Reuse) 5/27/2010
Power Management for Optimal Power Design (EDN Magazine) 5/27/2010
Selecting the Right Nonvolatile Memory IP: Applications and Alternatives (EE Times Embedded) 5/24/2010
The "Off-the-Shelf" IPs for Today's SoCs (EE Times Embedded) 5/24/2010
Implementing PCI Express Bridging Solutions In an FPGA (Embedded Computing Design) 5/19/2010
Producing and Verifying Quality FPGA IP (Embedded Computing Design) 5/19/2010
Protecting FPGAs from Power Analysis Attacks (EE Times Programmable Logic Designline) 5/18/2010
Building Cost-Effective and Robust SOC-based Network Appliances (EE Times Embedded) 5/17/2010
A Novel Mesh Architecture for On-Chip Networks (Design & Reuse) 5/16/2010
Implementing Different Power Features In an IP (Design & Reuse) 4/29/2010
Integrating Analog Video Interface IP Into SoCs Delivers Superb Image Quality: Part 2 (EE Times EDA Designline) 4/29/2010
An Analysis of Blocking versus Non-Blocking Flow Control In On-Chip Networks (Design & Reuse) 4/22/2010
Choosing the Best Standard Cell Library without Falling Into the Traps of Traditional Benchmarking Methods (Design & Reuse) 4/22/2010
Scratching the Surface: The 2010 EDN DSP Directory (EDN Magazine) 4/22/2010
An Application-Specific Processor for Many-Core Architectures (Design & Reuse) 4/15/2010
Incorporating Quality Into Reusable Interface IP (Design & Reuse) 4/15/2010
Integrating Analog Video Interface IP Into SOCs Delivers Superb Image Quality: Part 1 (EE Times EDA Designline) 4/7/2010
A Step-By-Step Methodical Approach for Efficient Mixed-Language IP Integration (Design & Reuse) 3/22/2010
Building Quality Assurance Into Your Hardware: EDA Is Not Enough! (EE Times EDA Designline) 3/17/2010
Selecting an Embedded MCU: How to Avoid the Evaluation Trap? (Design & Reuse) 3/11/2010
Embedded Symmetric MultiProcessing System On a SoC with 1.6GHz PowerPC IP in 45nm (Design & Reuse) 3/4/2010
Evolving to a Total IP Solutions to Accelerate SOC Design (Design & Reuse) 3/4/2010
Incorporating Quality Into Reusable IP (EE Times Embedded) 2/26/2010
Hardware Solutions to the Challenges of Multimedia IP Functional Verification (Design & Reuse) 2/25/2010
Software Architecture for IP verification in Operating System Environment (Design & Reuse) 2/25/2010
Reusable VHDL IP In the Real World (Design & Reuse) 2/18/2010
Guidelines for Complex SOC Verification (EE Times EDA Designline) 2/15/2010
Re-Configurable Platform for Design, Verification and Implementation of SOCs (Design & Reuse) 2/11/2010
Tools Accurately Simulate Noise in Mixed-Signal ASICs (EDN Magazine) 2/4/2010
Improving Software Development and Verification Productivity Using IP-Based System Prototyping (Design & Reuse) 2/1/2010
Increasing Bandwidth In Industrial Applications with FPGA Co-Processors (EE Times Programmable Logic Designline) 2/1/2010
A Recipe for Verification IP: The Role of Methodology (Design & Reuse) 1/26/2010
A Nuts and Bolts Engineering Approach to Using Open Source IP (EE Times Embedded) 1/25/2010
Designing Serial ATA IP Into Your Embedded Storage Device Design (EE Times Embedded) 12/14/2009
The Evolving Landscape of Digital Signal Processing (EDN Magazine) 12/3/2009
The Best of Both Worlds: Optimizing OCP Slave Memory Behavior (EE Times EDA Designline) 11/19/2009
Graphics Processing: When DIY Just Doesn't Make Sense (EE Times EDA Designline) 11/15/2009
What If the IP You Are Looking for Does Not Exist? (Design & Reuse) 10/29/2009
A Set of VHDL IPs to Evaluate Performance of Netwoks-on-Chip (Design & Reuse) 10/22/2009
Implementing an All-Digital PHY and Delay-Locked Loop for High-Speed DDR2/3 Memory Interfaces (EDN Magazine) 10/15/2009
Use of an IP core Development Process to Achieve Time-to-Market and Quality Assurance in a Multi-Project Environment (Design & Reuse) 10/15/2009
Outsourcing SoC Network Design Just Makes Sense (Electronic Design Magazine) 10/11/2009
IP Quality Lies Beyond Compliance Testing (EDN Magazine) 10/8/2009
Using Tcl to Create a Virtual Component in Verilog (EE Times Embedded) 10/2/2009
How FPGAs Can Address MCUs' General-Purpose I/O Scaling Wall (EE Times Programmable Logic Designline) 9/9/2009
Improving Software Driver Development and Hardware Verification Productivity using Virtual Platforms (Design & Reuse) 8/27/2009
Placement of Different Type Nodes In a Network-on-Chip Graph (Design & Reuse) 8/13/2009
First-Pass Success In Silicon Packaging (EDN Magazine) 8/6/2009
Techniques for Implementing High-Performance Processor Cores (EDN Magazine) 8/6/2009
Changing SoC Design Methodologies to Automate IP Integration and Reuse (EE Times EDA Designline) 7/27/2009
Virtual Multi-Cores Simplify Real-Time System Design (EE Times Embedded) 7/27/2009
Versatile OTP Can Replace Several Memories (Chip Estimate Corp.) 7/15/2009
Debugging Hybrid FPGA Logic/Processor Designs (Electronic Products Magazine) 7/1/2009
Should Dual-Rail Go Mainstream in Deep Nanometer Era? (Electronic Design Magazine) 6/29/2009
Little-Known Flash-Memory Features Protect Data and IP (EDN Magazine) 6/25/2009
SuperSpeed USB 3.0: Ubiquitous Interconnect for Next Generation Consumer Applications (Design & Reuse) 6/22/2009
Generic and Automatic Specman-based Verification Environment for Image Signal Processing IPs (Design & Reuse) 6/18/2009
SpiritEd: A Register Specification System integrating IP-XACT and Adobe FrameMaker (Design & Reuse) 6/18/2009
Designing Portability Into Silicon IP (EDN Magazine) 6/11/2009
Tailored SoC Building Using Reconfigurable IP Blocks (Design & Reuse) 6/8/2009
From IP Re-use to Open Innovation - A New Trend in the Industry (Design & Reuse) 6/4/2009
H.264/AVC HDTV Motion Compensation Soft IP (Design & Reuse) 6/4/2009
Software Interface Standard Gives New Framework (Electronic Products Magazine) 6/1/2009
A 0.79-mm2 29-mW Real-Time Face Detection IP Core (Design & Reuse) 5/25/2009
A Reusable Level 2 Cache Architecture (Design & Reuse) 5/25/2009
Processor Architecture Not a Factor for Low-Power Mobile Systems (EE Times Signal Processing DesignLine) 4/20/2009
Protecting Software IP: What Engineers Need to Know (Electronic Engineering Times (EE Times)) 4/20/2009
Building Advanced Cortex-M3 Applications (EE Times Embedded) 4/8/2009
Debug and Testability Features for Multi-Protocol 10G SerDes (Design & Reuse) 3/9/2009
Analog IP Integration in SoCs: Challenges and Solutions (Design & Reuse) 3/3/2009
How to Control Analog Output from a CPLD Using a Pulse Width Modulator (EE Times Programmable Logic Designline) 2/24/2009
How High-Level Synthesis Can Raise the Efficiency of Design Reuse (Design & Reuse) 2/23/2009
Refactoring to Prepare RTL for Reuse (Design & Reuse) 2/16/2009
Migrating From SPI 4.2 To SPI 5 IP Core: Architectural Changes and Reusability (Design & Reuse) 2/9/2009
Trailblazing SuperSpeed USB Design and Verification (Electronic Design Magazine) 1/29/2009
Identifying IP cores to Protect Your Investment (Design & Reuse) 1/26/2009
Modern ADCs Improve CMOS Image Sensors (EDN Magazine) 1/22/2009
The Value of High-Quality IP-XACT XML (Design & Reuse) 1/19/2009
An Application Modeling and Hardware Description for Network-on-Chip Benchmarking (EE Times Embedded) 1/14/2009
Architecting the OCP uVC Verification Component (EE Times EDA Designline) 1/13/2009
Taking the Delay Out of Your Multicore Design'S Intra-Chip Interconnections (EE Times Embedded) 1/7/2009
Verification IP: Solace for the Common Integration Nightmare? (New Tech Press) 12/24/2008
Planning, Adopting and Implementing Adaptive Reuse (EE Times EDA Designline) 12/16/2008
Planning, Adopting and Implementing Adaptive Reuse (EE Times EDA Designline) 11/18/2008
A SystemC/TLM Based Methodology for IP Development and FPGA Prototyping (EE Times EDA Designline) 11/3/2008
Choosing the Right Processor Candidate: the 35th Annual EDN Microprocessor Directory (EDN Magazine) 10/30/2008
Multicore: the Future of SOCs? (EDN Magazine) 10/30/2008
Taking the Broad View (Components in Electronics (CIE)) 10/1/2008
How to Defend Against The Cloning of Your FPGA Designs (EE Times Programmable Logic Designline) 9/17/2008
Building a Configurable Embedded Processor (EE Times Embedded) 9/9/2008
Debunking Multicore Design Complexities (Electronic Products Magazine) 9/1/2008
The Five Forces Driving the Semiconductor IP Market (Electronic Products Magazine) 9/1/2008
On-Chip Test Capabilities Solve the Analog-Test Problem for High-speed Serial Interfaces (EDN Magazine) 8/21/2008
Build Debug and Trace Systems for Multicore SOCs (Electronic Design Magazine) 8/14/2008
Learning Not to Fear PCI Express Compliance (EE Times EDA Designline) 8/12/2008
Protect Your FPGA Against Piracy (Electronic Design Magazine) 7/10/2008
RF: Will It Ever Be Plug-In IP? (EDN Magazine) 6/12/2008
Serial ATA and the Evolution in Data Storage Technology (EE Times EDA Designline) 4/28/2008
Integrating PCIe On-Chip (Electronic Products Magazine) 4/14/2008
Specifying Transceivers for Serial Protocols (Electronic Products Magazine) 4/14/2008
Interfacing High-Performance 32-bit Cores to MCU-based Memory Architectures (EE Times Embedded) 4/10/2008
Reducing Power in Embedded Systems by Adding Hardware Accelerators (EE Times Embedded) 4/9/2008
Implement a Complete ARV Controller in a Single SOC (Electronic Design Magazine) 3/27/2008
Using FPGAs to Avoid Microprocessor Obsolescence (EE Times Programmable Logic Designline) 3/5/2008
Low-Power Design for Analog/Mixed-Signal IP (EE Times EDA Designline) 3/4/2008
Comparing IP Integration Approaches for FPGA Implementation (EE Times Programmable Logic Designline) 2/20/2008
Multi-language Functional Verification Coverage for Multi-site Projects (EE Times EDA Designline) 2/18/2008
Automated Formal Verification of OCP-Based IP Cores (EE Times EDA Designline) 1/21/2008
A Chip IP Integrator for System Level Design (Design & Reuse) 1/14/2008
USB Host IP-Core Hardware and Software Concurrent Development (Design & Reuse) 1/10/2008
OCP VIP: A Cost-Effective and Robust Qualification Process for Multimedia and Telecom SOC Designs (EE Times Embedded) 1/9/2008
Dealing with the Challenges of Integrating Hardware and Software Verification (EE Times Embedded) 1/4/2008
Lower the Cost of Intelligent Power Control with FPGAs (EE Times Embedded) 12/15/2007
Designing DDR3 SDRAM Controllers with Today's FPGAs (EE Times Programmable Logic Designline) 12/12/2007
4G Wireless: Evolution or Watershed in SOC Architectures? (EDN Magazine) 10/4/2007
Regression Test for OCP SystemC Channel Models (EE Times EDA Designline) 9/4/2007
A Bluespec Hardware Implementation of Sudoku (EE Times EDA Designline) 8/21/2007
Verification Methodologies Keep Pace with Complex IP (EE Times EDA Designline) 8/14/2007
Achieving Certified IP Quality Efficiently (EE Times EDA Designline) 5/29/2007
Verifying Configurable Verification Interfaces Using OCP (EE Times EDA Designline) 5/10/2007
Analog and Mixed-Signal Connectivity IP at 65nm and Below (EE Times EDA Designline) 5/7/2007
Video Codecs in SOCs Using OCP-Based Programmable Accelerator Design (Video/Imaging DesignLine) 4/27/2007
Rigorous Automated Verification Yields High Quality Silicon (EE Times EDA Designline) 4/24/2007
The Growing Need for Secure Storage in Automotive Systems (EE Times EDA Designline) 4/6/2007
Choosing to Use an SIP Rather than an SOC (EDN Magazine) 3/15/2007
FPGA Design Issues 201 (Electronic Design Magazine) 3/15/2007
Achieving Completeness in IP Functional Verification (EE Times EDA Designline) 2/12/2007
Evaluating IP with the Four Cs: Compare, Consider, Collect, and Calculate (EDN Magazine) 2/1/2007
A Logical Approach to NVM Integration in SOC Design (EDN Magazine) 1/18/2007
Utilizing OCP to Design a High Performance Interconnect (EE Times EDA Designline) 1/18/2007
Good Or No Good? An Insider Look at What Works for ESL (Electronic Design Magazine) 12/15/2006
Embedded Memory Evolves (EDN Magazine) 12/1/2006
Proprietary Architectures Defend Automotive Space (EDN Magazine) 12/1/2006
IP Plays Cautiously in Emerging Markets (EDN Magazine) 11/9/2006
How to Increase Confidence that Third-Party IP is Functionally Correct (EE Times EDA Designline) 10/1/2006
Verification IP Takes a Broader Role (eeDesign (EE Times EDA News)) 8/7/2006
EDN 2006 Microprocessor Directory (EDN Magazine) 8/3/2006
OCP "Tags" Support High-Performance SoCs (eeDesign (EE Times EDA News)) 5/8/2006
A Hierarchy of Needs for SoC IP Reuse (eeDesign (EE Times EDA News)) 4/17/2006
IP Integration Is Standard Fare (Electronic Design Magazine) 4/13/2006
Choosing Hardware IP (EE Times Embedded) 2/1/2006
Chip Assembly Challenges and Solutions (eeDesign (EE Times EDA News)) 1/23/2006
A Practical Approach to Reusing HDL Code in FPGA Designs (EE Times Programmable Logic Designline) 12/28/2005
Picking the Right RTOS for a Hybrid RISC/DSP Core (EE Times Embedded) 12/26/2005
OCP-Based Memory Access Arbitration for a Digital Sampling Oscilloscope (EE Times Programmable Logic Designline) 12/7/2005
FPGA Soft Processor Design Considerations (EE Times Programmable Logic Designline) 10/12/2005
Easing Verification Challenges for IP Reuse (eeDesign (EE Times EDA News)) 8/22/2005
Aggregation Drives Successful IP Reuse (Chip Design Magazine) 8/1/2005
An IP Storm? (EDN Magazine) 6/23/2005
IP Reuse Gets a Reality Check (Chip Design Magazine) 6/1/2005
On-Chip Nonvolatile Memory Proves Ideal for Consumer Applications (Chip Design Magazine) 5/1/2005
SPIRIT: Structure for Packaging, Integrating, and Re-Using IP within Tool Flows (Chip Design Magazine) 5/1/2005
Get the Lowdown On IP for Your Startup (Electronic Design Magazine) 4/14/2005
Outpace Your Competitors With a Solid IP Plan (Electronic Design Magazine) 4/14/2005
IP Reuse Requires a Verification Strategy (eeDesign (EE Times EDA News)) 2/8/2005
Third-Party IP: A Shaky Foundation for SOC Design (EDN Magazine) 2/3/2005
How Memory Architectures Affect System Performance (eeDesign (EE Times EDA News)) 1/31/2005

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Tutorials, Whitepapers & Application Notes on Intellectual Property

10 Tips for Successful SOC Design (Tensilica, Inc.)
A Guide to Understanding Optimized Processor Cores (Synopsys, Inc.)
A Memory Subsystem Model for Evaluating Network-on-Chip Performance (OCP International Partnership (OCP-IP))
A Methodology for Performance Analysis of Network-on-Chip Architectures for Video SoC (OCP International Partnership (OCP-IP))
A Processor and DSP IP Selection Checklist (Tensilica, Inc.)
A Survival Guide for Selecting High-Quality IP (Synopsys, Inc.)
Accelerating Functional Closure: Synopsys Verification Solutions (Synopsys, Inc.)
Addressing Power and Speed Requirements of Mobile Devices with Data Converter IP (Synopsys, Inc.)
Advanced Stimulus Generation with DesignWare Verification IP and Verification Methodology Manual for SystemVerilog (Synopsys, Inc.)
Advanced Techniques for Building Robust Testbenches with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog (Synopsys, Inc.)
Advanced Virtual Platform Validation Methodology (JEDA Technologies, Inc.)
An Initiative Towards Open Network-on-Chip Benchmarks (OCP International Partnership (OCP-IP))
An OCP TLM for Architectural Modeling (OCP International Partnership (OCP-IP))
Application Specific Programmable Platform Using eASICore (eASIC Corp.)
Benefits and Applications of the Wireless USB WHCI Host and Dual-Role Device (Synopsys, Inc.)
Best Practices for Maximizing IP Reuse in SOC, IC and FPGA Design (IC Manage, Inc.)
Beyond DDR2 400: Physical Implementation Challenges in Your SoC Design (Synopsys, Inc.)
Boost ASIC and SOC Performance by Matching Processor to Task through Automated Processor Generation (Tensilica, Inc.)
Building a Total Quality Experience into Silicon IP: Delivering DesignWare Silicon IP into SoC Designs (Synopsys, Inc.)
Coding Guidelines for Datapath Synthesis (Synopsys, Inc.)
Combining Impulse C with uClinux for MicroBlaze-based FPGAs (Impulse Accelerated Technologies, Inc.)
CONNECT: Re-Examining Conventional Wisdom for Designing NoCs in the Context of FPGAs (Carnegie Mellon Electrical & Computer Engineering)
CoRAM: An In-Fabric Memory Architecture for FPGA-based Computing (Carnegie Mellon Electrical & Computer Engineering)
C-To-CoRAM: Compiling Perfect Loop Nests to the Portable CoRAM Abstraction (Carnegie Mellon Electrical & Computer Engineering)
DDR SDRAM: A Low Cost, Yet Increasingly Complex Off-Chip Memory Solution for SoCs (Synopsys, Inc.)
Delivering Synthesizable Verification IP for Test Benches (Bluespec, Inc.)
Design Management & IP Reuse Study (Gary Smith EDA)
Designing Using the AMBA 3 AXI Protocol (Synopsys, Inc.)
DesignWare SATA AHCI Host Controller: Understanding Multi-Port Configuration and Performance (Synopsys, Inc.)
Embedded DDR Interfaces: Ten Tips to Success for Your SoC (Synopsys, Inc.)
Embedded SRAM Options for ASICs and SOCs (Novelics, Inc.)
Enabling Rapid Adoption of the AMBA 3 AXI Protocol-based Design with Synopsys DesignWare IP (Synopsys, Inc.)
Everything You Wanted to Know About SOC Memory (Tensilica, Inc.)
Examining ARM's Cortex Microcontroller Software Interface Standard (Feabhas, Ltd.)
Favorable Economics Will Drive Rapid Adoption of Certified Wireless USB (Synopsys, Inc.)
Five Vital Steps to a Robust Testbench with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog (Synopsys, Inc.)
FPGAs for Software Radio (Pentek, Inc.)
Global Design Management Report 2012 (IC Manage, Inc.)
Heterogeneous MP-SoC: The Solution to Energy-Efficient Signal Processing (CoWare, Inc.)
Hi-Fi Audio: Unveiling the Hidden dBs (Synopsys, Inc.)
High Performance Connectivity IP: Avoiding Pitfalls when Selecting an IP Vendor (Synopsys, Inc.)
Highest MHz Does Not Mean Highest Performance (Tensilica, Inc.)
How a Complete IP Solution Speeds Time-to-Market and Reduces Risk for 10-Gigabit Ethernet Applications (Synopsys, Inc.)
How System-Level Trade-Offs Drive Data Converter Decisions (Synopsys, Inc.)
How to Avoid the Traps and Pitfalls of SOC Design (Tensilica, Inc.)
How to Increase ASICs and SOC Computational Performance with Long-Word Processors (Tensilica, Inc.)
IC Design Management Best Practices (IC Manage, Inc.)
Implementing Floating-Point IP for the Right Accuracy and Quality of Results (QoR) (Synopsys, Inc.)
Implementing Physical Layer Connectivity IP in Deep Sub-Micron Technologies (Synopsys, Inc.)
Integrating a PCI Express Digital IP Core into a Gigabit Ethernet Controller (Synopsys, Inc.)
Intellectual Property Business Models (Mentor Graphics Corp.)
Interoperable IP Delivery (Aldec, Inc.)
IP Reuse and Design Management in the SOC and IC Design Process (Gary Smith EDA)
IP Reuse Creation for System-on-a-Chip Design (Mentor Graphics Corp.)
IP Reuse: Design and Verification Report 2013 (IC Manage, Inc.)
IP Solutions for Synchronizing Signals that Cross Clock Domains (Synopsys, Inc.)
Licensable Processors: More Than Just Design IP (StarCore)
Life Begins at 65 – Unless You Are Mixed-Signal? (Synopsys, Inc.)
Low-Power USB 2.0 PHY IP for High-Volume Consumer Applications (Synopsys, Inc.)
Meeting Timing Budgets for DDR Memory Interfaces (Synopsys, Inc.)
Modeling OCP Interfaces in SystemC: Standards built on top of OSCI’s TLM-2 (OCP International Partnership (OCP-IP))
Modular, Configurable Bus Architecture Targeted for Ease of IP Reuse on System-on-Chip and ASIC Devices (Portland State University, ECE Department)
Next-Generation Embedded Memory Performance (Memoir Systems, Inc.)
On-Chip Communications Network Report (Sonics, Inc.)
On-line Detection of Control-Flow Errors in SoCs By Means of an Infrastructure IP Core (Politecnico di Torino)
Phase-Change Memory Becomes a Reality (Objective Analysis)
Processor Core Power Specs: A Cautionary Tale (Tensilica, Inc.)
Processor Ports and Queues: Easily Overcome I/O-Bandwidth Obstacles in Your Next ASIC or SOC Design (Tensilica, Inc.)
Prototype and Evaluation of the CoRAM Memory Architecture for FPGA-based Computing (Carnegie Mellon Electrical & Computer Engineering)
Reduce Power, Area and Routing Congestion: Analysis of a High-Performance On-Chip-Bus Interconnect (Synopsys, Inc.)
Reducing AMBA-based SoC Design Time by More Than 50% Using coreAssembler (Synopsys, Inc.)
Reverse Disaggregation: How Silicon IP Will Change the Semiconductor Supply Chain (Synopsys, Inc.)
RFC (Recursive Flow Classification) ASIC IP Core (Calsoft Labs)
Routing Congestion (Arteris SA)
Secure Implementations of Content Protection (DRM) Schemes (Discretix Technologies, Ltd.)
Si2 Power Aware Design Flows (Silicon Integration Initiative, Inc. (Si2))
Si2 Power Reduction Stimulus and Low Power Design Techniques (Silicon Integration Initiative, Inc. (Si2))
Single-chip Heterogeneous Computing: Does the Future include Custom Logic, FPGAs, and GPUs? (Carnegie Mellon Electrical & Computer Engineering)
Socket-Centric IP Core Interface Maximizes IP Applications (OCP International Partnership (OCP-IP))
Soft CPU Cores for FPGA (1-CORE Technologies)
Solving the Integration Challenges for USB-Enabled Designs (Synopsys, Inc.)
Standard Debug Interface Socket Requirements for OCP-Compliant SoCs (OCP International Partnership (OCP-IP))
Straightforward IP Integration with IP-XACT RTL-TLM Switching (IPsupermarket)
Technology: Develop Or License? (StarCore)
The Evolution of Embedded Memory and 3D Packaging (weSRCH)
The Good? The Bad? The Ugly? IP Perspectives from Vendor to SoC Integrator (Synopsys, Inc.)
The Importance of Sockets in SOC Design (OCP International Partnership (OCP-IP))
The Open Verification Methodology (OVM), (OVM World)
The SoC Interconnect Verification Challenge (Test and Verification Solutions, Ltd. (TVS))
The What, Why, and How of Configurable Processors (Tensilica, Inc.)
Three SOC Application Segments Require Embedded OTP Memory (Kilopass Technology, Inc.)
Understanding the Fundamentals of PCI Express (Synopsys, Inc.)
Unifying Bug Tracking with Design-Data Management (IC Manage, Inc.)
Using IC Manage GDP for Collaborative Custom IC (Virtuoso) and Digital SOC Design (IC Manage, Inc.)
Using Impulse C with BlueCat Linux 5.4.2 on MicroBlaze via FSL (Impulse Accelerated Technologies, Inc.)
Using Processors in the SOC Dataplane (Tensilica, Inc.)
Verification and Automation Improvement Using IP-XACT (Accellera)
Viterbi Algorithm for Decoding of Convolutional Codes (1-CORE Technologies)
What Is Verification IP? (Tech Design Forum)
Xtensa Architecture and Performance (Tensilica, Inc.)

(back to top)


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