Page loading . . .

 Category: Tutorials, White Papers, App Notes, etc.: Wednesday, July 01, 2015
 Tutorials, White Papers, Application Notes, etc.

The Internet is very much like the Metropolitan Museum of Art; what you see on display is only a small fraction of what's hidden in the bowels of the basement. To find the "treasures" hidden in the bowels of EDA tool and IP vendors' "basements," SOCcentral drills down into their websites to seperate the tutorials, white papers, and generic app notes from the marketing hype and product brochures.

Know of a white paper or app note that would interest visitors?

If you do, we'd like to know about it! If it meets our criteria, we'll add an abstract to our database and provide the appropriate link to the white paper or app note. Please send your recommendations to

Recommended Tutorials, White Papers, etc.

On-Chip Communications Network Report (Sonics, Inc.)

This report covers the results of an independent, blind worldwide survey covering on-chip communications networks (OCCN), defined as is the entire interconnect fabric for SOCs. The survey was executed in October 2012, with 318 design and verification professionals participating. . . . read more

The SoC Interconnect Verification Challenge (Test and Verification Solutions, Ltd. (TVS))

With increasing numbers of CPU cores, multimedia subsystems and communication IPs in today's system-on-chips, the main SOC interconnects, crossbars or networks-on-chip fabrics become key components of the system. In addition, IP reuse and network-on-chip (NoC) generation solutions have enabled the conception of new SoC architectures within a few months if not only weeks. . . . read more

VHDL PaceMaker Interactive Tutorial (Doulos, Ltd.)

VHDL PaceMaker is a self-teach tutorial that gives you a great foundation in the basics of the VHDL language. VHDL PaceMaker is ideally suited to self-paced learning prior to attending full-scope instructor-led VHDL training. As well as serving as an introductory tutorial, VHDL PaceMaker, with its interactive hyperlinks, provides an excellent interactive reference tool for the VHDL designer. It includes a full syntax reference, a glossary of technical terms, and the ability for you to annotate your own notes. . . . read more

Design-for-Test Guidelines (Corelis, Inc.)

In today's fast-paced environment with short time-to-market requirements, it has become increasingly important to design products that allow for early fault and failure detection. The earlier a mistake or a defect can be detected in the design phase or in the production process, the less money it will cost to remedy it and the sooner the product will be ready for production or shipment. Therefore, a good design-for-test (DFT) strategy is needed for the design, prototype and production phase of a product. . . . read more

Variation-Aware Custom IC Design Report 2011 (Solido Design Automation, Inc.)

This report covers the results of an independent worldwide custom IC design survey. The survey was executed in late 2010, with 486 IC design professionals participating. . . . read more

FPGA Design Tutorial (1-CORE Technologies)

This FPGA design tutorial covers various issues in the fields of FPGA design, simulation and synthesis. It is targeted towards both beginners and experienced FPGA designers. . . . read more

What's the difference between Tutorials, White Papers, and App Notes?

Search Tutorials, White Papers, etc.
 Find all:
White Papers
Application Notes

View all Tutorials, White Papers, etc.

 White Papers
 Application Notes

Selecting a specific Category will generate an alphabetical listing* of ALL the entries in that Category.

* SOCcentral's Sponsors' white papers, app notes, etc. are listed first.

10 Most-Read White Papers
Archipelago: An Open Source FPGA with Toolflow Support

Most-Read Recent News (updated daily)
Algo-Logic Systems Launches 40-Gbps TCP End-Point on Altera Stratix V for Datacenter Acceleration
Catena Partners with CEVA for Complete Wi-Fi and Bluetooth Solutions for Mobile, Wearable and IoT Devices
CEVA Unveils Wi-Fi IP Platforms to Enable a Broad Range of Connected Devices
Beken Adopts CEVA DSP and Connectivity IPs for Its Wireless Audio SOC Roadmap
GOEPEL electronics Protects Intellectual Property in Xilinx FPGAs
Keysight Technologies Announces Asygn's, Kalray's Successful Use of Its Simulation Tool Suite to Validate PCI Express Gen3 Serial Links
Freescale Takes Its Next-Generation QorIQ Multi-Core Platform to 16-nm FinFET Technology
Algo-Logic Systems Launches 40-Gbps TCP End-Point on BittWare S5-PCIe-HQ FPGA Board
eASIC and Comcores Deliver CPRI v6.1 Switch Reference Design for Next-Generation LTE Advanced and 5G Networking Equipment
AMD Embedded G-Series SOC Powers New Line of Samsung All-in-One Thin-Client Solutions

Suggested Tutorials, White Papers, etc.

Tutorials, White Papers, etc. abstracted since Wednesday, January 14, 2015

A Cooperative Simulation Formal Methodology: Target Verification with Both Barrels (Test and Verification Solutions, Ltd. (TVS))

Applying Agile Techniques to FPGA Development (Test and Verification Solutions, Ltd. (TVS))

Can We Train Our Designers to Avoid Bugs? (Test and Verification Solutions, Ltd. (TVS))

Continuous Integration for FPGA Design and Verification (Test and Verification Solutions, Ltd. (TVS))

FPGA-based Prototyping Tackling Large Designs Earlier (Test and Verification Solutions, Ltd. (TVS))

Predictable Verification Productivity (Test and Verification Solutions, Ltd. (TVS))

Reducing the Cost of FPGA/ASIC Verification with MATLAB and Simulink (Test and Verification Solutions, Ltd. (TVS))

Requirements-Driven Verification for Compliance (Test and Verification Solutions, Ltd. (TVS))

SystemC-based UVM Verification Infrastructure (Test and Verification Solutions, Ltd. (TVS))

Verification IP Trends and Technology for FPGA and ASIC Design Verification (Test and Verification Solutions, Ltd. (TVS))

Designer's Mall


 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
and receive news, article, whitepaper, and product updates bi-weekly.


Verification Contortions

Dr. Lauro Rizzatti
Verification Consultant
Rizzatti, LLC

Real Talk

P2415: The New Power Standard for Unified Hardware Abstraction

Graham Bell
VP Marketing
Real Intent

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
DSP Design
Analog Design
Digital Design
Mixed-Signal Design
RF Design
EDA Tool Development

IC Packaging
PCB Design
RTOS Development
RTL Design
SystemC Design
SystemVerilog Design
Verilog Design
VHDL Design

Post a Job
Only $100 for 30 days

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Design Center
Tutorials, Whitepapers & App Notes
Archived Webcasts


Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
188  0.140625