Page loading . . .

  
 Category: Tutorials, White Papers, App Notes, etc.: Tuesday, September 02, 2014
 Tutorials, White Papers, Application Notes, etc.

The Internet is very much like the Metropolitan Museum of Art; what you see on display is only a small fraction of what's hidden in the bowels of the basement. To find the "treasures" hidden in the bowels of EDA tool and IP vendors' "basements," SOCcentral drills down into their websites to seperate the tutorials, white papers, and generic app notes from the marketing hype and product brochures.

Know of a white paper or app note that would interest SOCcentral.com visitors?

If you do, we'd like to know about it! If it meets our criteria, we'll add an abstract to our database and provide the appropriate link to the white paper or app note. Please send your recommendations to directory_editor@soccentral.com.


Recommended Tutorials, White Papers, etc.

On-Chip Communications Network Report (Sonics, Inc.)

This report covers the results of an independent, blind worldwide survey covering on-chip communications networks (OCCN), defined as is the entire interconnect fabric for SOCs. The survey was executed in October 2012, with 318 design and verification professionals participating. . . . read more

The SoC Interconnect Verification Challenge (Test and Verification Solutions, Ltd. (TVS))

With increasing numbers of CPU cores, multimedia subsystems and communication IPs in today's system-on-chips, the main SOC interconnects, crossbars or networks-on-chip fabrics become key components of the system. In addition, IP reuse and network-on-chip (NoC) generation solutions have enabled the conception of new SoC architectures within a few months if not only weeks. . . . read more

VHDL PaceMaker Interactive Tutorial (Doulos, Ltd.)

VHDL PaceMaker is a self-teach tutorial that gives you a great foundation in the basics of the VHDL language. VHDL PaceMaker is ideally suited to self-paced learning prior to attending full-scope instructor-led VHDL training. As well as serving as an introductory tutorial, VHDL PaceMaker, with its interactive hyperlinks, provides an excellent interactive reference tool for the VHDL designer. It includes a full syntax reference, a glossary of technical terms, and the ability for you to annotate your own notes. . . . read more

Design-for-Test Guidelines (Corelis, Inc.)

In today's fast-paced environment with short time-to-market requirements, it has become increasingly important to design products that allow for early fault and failure detection. The earlier a mistake or a defect can be detected in the design phase or in the production process, the less money it will cost to remedy it and the sooner the product will be ready for production or shipment. Therefore, a good design-for-test (DFT) strategy is needed for the design, prototype and production phase of a product. . . . read more

Variation-Aware Custom IC Design Report 2011 (Solido Design Automation, Inc.)

This report covers the results of an independent worldwide custom IC design survey. The survey was executed in late 2010, with 486 IC design professionals participating. . . . read more

FPGA Design Tutorial (1-CORE Technologies)

This FPGA design tutorial covers various issues in the fields of FPGA design, simulation and synthesis. It is targeted towards both beginners and experienced FPGA designers. . . . read more

What's the difference between Tutorials, White Papers, and App Notes?

 
Search Tutorials, White Papers, etc.
 Find all:
Tutorials
White Papers
Application Notes
Presentations
 

View all Tutorials, White Papers, etc.

 Tutorials
 White Papers
 Application Notes
 Presentations

Selecting a specific Category will generate an alphabetical listing* of ALL the entries in that Category.

* SOCcentral's Sponsors' white papers, app notes, etc. are listed first.


10 Most-Read White Papers
CDC Methodology for Fast-to-Slow Clocks
Magic of SDN in Networking
RFID: Solutions without a Barrier

Most-Read Recent News (updated daily)
Cypress and HLMC Demonstrate Working Silicon Cells Leveraging 55-nm Embedded Flash IP
Northwest Logic's PCI Express Gen3 Core and S2C's Virtex-7 ASIC Prototyping Platform Fully Validated Together
New Single-Core C2000 Delfino F2837xS microcontrollers Bring 16-bit ADC Precision to Industrial Control Applications
Altera Plans Full Compliance with Military Temperature Specification for 20-nm FPGA and SOC Devices
Mentor Graphics Extends Nucleus RTOS with Industry-Leading Capabilities for Microcontroller and Multi-core Applications
Real Intent Signs Quantum Leap Sales as Sales Partner for the U.S.
FURUNO Electric Reduces Design Time by 40% Using NI AWR Design Environment and LabVIEW
HIREC Renews Silvaco's TCAD and EDA Tool Licenses for Designing High-Reliability LSIs
Maxscend Partners with CEVA to Offer Complete Wi-Fi and Bluetooth Solutions for Mobile Platforms, Wearables and IoT Devices
3D IC Expands in New Dimensions at Si2
Altera Releases Quartus II Software Arria 10 Edition v14.0
Sunstone Circuits Announces PCB123 Version 5.1.0
Cypress Adds Support for Single-Layer Sensors and Gloved-Finger Tracking to TrueTouch Gen4X Touchscreen Controller Family
JEDEC Releases LPDDR4 Standard for Low-Power Memory Devices
Dongbu HiTek Streamlines Touch Control for Smart Phones

Suggested Tutorials, White Papers, etc.


Tutorials, White Papers, etc. abstracted since Tuesday, March 18, 2014



Designer's Mall
Halloween countdown banner

0.328125



 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Executive
Viewpoint

Progressive Static Verification Leads to Earlier and Faster Timing Sign-off


Graham Bell
VP of Marketing,
Real Intent

Odd Parity

Summertime and the Leavin' Ain't Easy


Mike Donlin
The Write Solution

Odd Parity Archive

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters



About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
188  0.46875