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 Category: Tutorials, White Papers, App Notes, etc.: Friday, April 18, 2014
 Tutorials, White Papers, Application Notes, etc.

The Internet is very much like the Metropolitan Museum of Art; what you see on display is only a small fraction of what's hidden in the bowels of the basement. To find the "treasures" hidden in the bowels of EDA tool and IP vendors' "basements," SOCcentral drills down into their websites to seperate the tutorials, white papers, and generic app notes from the marketing hype and product brochures.

Know of a white paper or app note that would interest visitors?

If you do, we'd like to know about it! If it meets our criteria, we'll add an abstract to our database and provide the appropriate link to the white paper or app note. Please send your recommendations to

Recommended Tutorials, White Papers, etc.

On-Chip Communications Network Report (Sonics, Inc.)

This report covers the results of an independent, blind worldwide survey covering on-chip communications networks (OCCN), defined as is the entire interconnect fabric for SOCs. The survey was executed in October 2012, with 318 design and verification professionals participating. . . . read more

The SoC Interconnect Verification Challenge (Test and Verification Solutions, Ltd. (TVS))

With increasing numbers of CPU cores, multimedia subsystems and communication IPs in today's system-on-chips, the main SOC interconnects, crossbars or networks-on-chip fabrics become key components of the system. In addition, IP reuse and network-on-chip (NoC) generation solutions have enabled the conception of new SoC architectures within a few months if not only weeks. . . . read more

VHDL PaceMaker Interactive Tutorial (Doulos, Ltd.)

VHDL PaceMaker is a self-teach tutorial that gives you a great foundation in the basics of the VHDL language. VHDL PaceMaker is ideally suited to self-paced learning prior to attending full-scope instructor-led VHDL training. As well as serving as an introductory tutorial, VHDL PaceMaker, with its interactive hyperlinks, provides an excellent interactive reference tool for the VHDL designer. It includes a full syntax reference, a glossary of technical terms, and the ability for you to annotate your own notes. . . . read more

Design-for-Test Guidelines (Corelis, Inc.)

In today's fast-paced environment with short time-to-market requirements, it has become increasingly important to design products that allow for early fault and failure detection. The earlier a mistake or a defect can be detected in the design phase or in the production process, the less money it will cost to remedy it and the sooner the product will be ready for production or shipment. Therefore, a good design-for-test (DFT) strategy is needed for the design, prototype and production phase of a product. . . . read more

Variation-Aware Custom IC Design Report 2011 (Solido Design Automation, Inc.)

This report covers the results of an independent worldwide custom IC design survey. The survey was executed in late 2010, with 486 IC design professionals participating. . . . read more

FPGA Design Tutorial (1-CORE Technologies)

This FPGA design tutorial covers various issues in the fields of FPGA design, simulation and synthesis. It is targeted towards both beginners and experienced FPGA designers. . . . read more

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Selecting a specific Category will generate an alphabetical listing* of ALL the entries in that Category.

* SOCcentral's Sponsors' white papers, app notes, etc. are listed first.

10 Most-Read White Papers
Best Practices for Maximizing IP Reuse in SOC, IC and FPGA Design
Challenges in Verification of Clock Domain Crossings
CDC Methodology for Fast-to-Slow Clocks
Clock Domain Crossing Demystified: The Second Generation Solution for CDC Verification
Multicore Programming Practices (MPP) Guide
Using Plots for HDL Debugging as a Powerful Alternative to Traditional Waveforms
IP Reuse: Design and Verification Report 2013
Using IC Manage GDP for Collaborative Custom IC (Virtuoso) and Digital SOC Design
ARM Cortex SoC Prototyping Platform for Industrial Applications
Making Floating-Point Arithmetic Work in Your RTL Design

Most-Read Recent News (updated daily)
HDL Design House Announces JESD204B PCS Tx IP Core HIP 600
TI Delivers First Sitara Software Development Kit Based on a High-Quality, Stable Mainline Linux kernel
intoPIX Bridges Professional Video Production and Ethernet Networks with New AVB FPGA IP Cores
Imagination's PowerVR Series6 GPU Passes OpenCL 1.2 Conformance with Khronos
Marvell Releases New 28-nm 10GbE and GbE Packet Processor Product Suite
Semiconductor IP Market Worth $5.63 Billion by 2020
Shikino Launches Still-Image Encoder IP for High-Speed Image Processing in 16X Speed
SpaceStudio Hardware/Software Codesign Tool Expands Offering to New SOC Design Markets
Jasper Launches Sequential Equivalence Checking App to Formally Verify Functional Equivalence of RTL Implementations
TowerJazz Announces Completion and Kick-off of Joint Venture with Panasonic
Microchip Introduces Cost-Effective 8-bit PIC Family with Intelligent Analog and Core-Independent Peripherals
Mentor Graphics Announces the Questa X-Value Verification Solution
Xilinx Enables "Softly" Defined Networks with New Software Defined Specification Environment
EDA Consortium Reports Revenue Increase for Q4 2013
AMD and Mentor Graphics to Accelerate Open-Source Linux Development for Embedded Systems

Suggested Tutorials, White Papers, etc.

Tutorials, White Papers, etc. abstracted since Friday, November 01, 2013

CDC Methodology for Fast-to-Slow Clocks  (Real Intent, Inc.)

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