March 18, 2005 -- As mask costs push higher for each new technology node, fundamental shifts are occurring in the tradeoff between the various cost components of technology development. The time it takes to generate parametric test chips can be a significant determinant of the time-to-market for new products and thus a determinant of profitability. Once generated, errors in test chips, and the subsequent analysis of the data produced by errors, also eat into time and profitability, making it imperative to reduce errors at creation.

In this environment of increasing costs, optimizing the efficiency of test chips for technology development has taken on a new importance. And the need for an automated process for test chip creation continues to grow.

Brute force methods for test chip creation are costly and error-prone.

The typical brute force approach to test chip creation involves hand crafting of test device layouts. This is a workable solution for small test chips where speedy delivery of a completed test chip is not on the critical path for technology development. However, this approach is inefficient for cases involving large numbers of test devices, where time to creation is critical, and where errors in test device layout can be extremely costly. With the increasing time pressure and expense of new technology nodes, opportunities for delay and error become even more critical. In addition, complex technologies such as analog-mixed signal, which require numerous variations in test devices to support multiple operating voltages, also require improved solutions to support the large number of test structures.

The block diagram in Figure 1 illustrates this process.

Figure 1. Each of the interfaces here represents a source of possible error from misinterpretation of the information being exchanged.

Common Problems of Test Chip Creation

A few of the common problems that plague parametric test chip creation and that are costly to handle with brute force approaches include:

Last minute revisions to test chips, which often require a complete re-work: This is an issue because there is frequently ongoing engineering effort to revise the rules and dimensions included in the test chip. When improved information becomes available, it is often late in the test chip development cycle. Lack of re-usability from prior test chip iterations: Oftentimes, the requirements for a new generation or process shrink begin with simple adjustments to critical dimensions. Without an automated process for test chip creation, these simple changes, just like the last minute revisions mentioned above, require a complete re-working of the test chip. Errors in test device layout produce incorrect conclusions from measured results: Manual device layout can produce errors in the structures that stem from human error during the layout of the test chip. These can amount to random defects or they can be systematic. In either case, these structural errors are hard to isolate. There is always a significant danger that errors in the layout of individual devices will produce results that are skewed or even completely contrary to results produced by correct device layouts. Documentation errors produced by hand-crafted documentation: Documentation errors can produce the same kinds of problems as layout errors since the conclusions drawn by engineers analyzing the electrical test results from the test chip may be erroneous. Inconsistency between test chip devices and parameterized cells provided to designers: A critical step follows the selection of desired test device layouts -- the conversion of the attributes of the selected devices into a parameterized cell. If the parameterized cell is not consistent with the original test devices, the optimum device may not be provided to the designers.

Automation offers solutions to common problems

Many of the problems highlighted above can be addressed through increased automation in the test chip creation process. For example, by creating parameterized devices as part of the test chip creation process, and coupling these with an automated place and route routine (along with standard pad ring components) test chip revision can be a trivial operation, with the bulk of the work performed by software. Using this approach, the complete test chip can be regenerated automatically for changes to a device dimension or design rule value.

Automation also makes possible the re-use of proven IP in the form of parameterized devices from previous iterations. If properly constructed, these parameterized devices can be flexible enough to be used for a wide range of critical dimensions.

Finally, a comprehensive automated system for test chip generation can automatically produce parameterized cells from the parameterized devices used to create the test chips. This guarantees consistency between test chips and design components as well as creating the potential to generate consistent parameterized cells for multiple target design environments.

With automation, the potential for human errors in layout or documentation can be dramatically reduced or eliminated altogether.

The importance of object-oriented re-use of devices and device elements

The use of hierarchical elements in test device structures adds another aspect to re-usability and automation because it allows elements to be verified and re-used across multiple device types. Constructing test structures using hierarchical elements promotes re-use on both device and device feature levels.

Time to completion of a project can be improved by splitting the task into a hierarchical tree of objects. The smaller sections of the task can then be developed and tested separately, possibly by field specialists. Once completed, a section can be re-used in another structure with confidence. Ever larger structures and sub-circuits then can be easily constructed by re-using elements that are already available.

The figure below illustrates one possible object-oriented schema for the re-use of elements to form devices or even small circuits.

Figure 2. One possible object-oriented schema for the re-use of elements to form devices or even small circuits.

One possible flow for creation of test chips in an automated environment

Figure 3 illustrates the basic attributes of a system for automated test chip generation. This approach reduces many of the errors highlighted above that result from the manual approach. In addition, it facilitates automated revision should errors or changes in the specification for the test chip occur after the initial setup costs.

Figure 3. Basic attributes of a system for automated test chip generation.

A practical example of this automated process occurred in a recent test chip project where a change to a design rule had to be implemented at the very last minute, just prior to mask creation for the test chip. In the manual approach used in the past, such a change would have required re-doing about 50% of the work of creating the test chip. Using the automated approach described above, the complete test chip was regenerated with the changed design rule within a matter of minutes. Result: the client saved several days of effort and avoided a potentially costly schedule slip.

Conclusion

Increasing cost and complexity of parametric test chips combined with increasing time sensitivity makes a review of current test chip generation approaches important. Automation presents an opportunity to reduce the cost of test chip creation, reduce errors in test chips and associated documentation, and, most importantly, an opportunity to re-use valuable IP created during initial test chip creation.

Object-oriented approaches further enhance the potential for re-usability, making automation possible at every level in the test chip creation process.

By Tim Crandle and Anthony Clark

Tim Crandle, Ph.D. is president of Stone Pillar Technologies, Inc. and has been developing and writing about semiconductor technology CAD for nearly twenty years.

Anthony Clark is CTO and co-founded Stone Pillar Technologies in 2000. He has led new product research and has been responsible for the capabilities that are presently in use in the Silicon Insight product suite.