April 19, 2005 -- Verific Design Automation, Inc. and Altium, Ltd. have announced that Altium is using Verific Design Automation's hardware description language (HDL) Component Software in Nexar, Altium's comprehensive, vendor-independent solution for embedded system-level design on an FPGA-platform. Verific's HDL Component Software includes C++ source code-based parsers, analyzers and elaborators for Verilog and VHDL that are tightly integrated with Nexar.

Altium recently announced the expansion of HDL capabilities of Nexar with the introduction of support for Verilog through a license agreement with Verific to use its HDL Component Software. Designers using Nexar now have complete freedom in the choice of capture language. They can use any combination of block diagram, VHDL and Verilog to capture circuit hardware for FPGA implementation.

Using Nexar, designers require little or no experience using HDLs or RTL source code in order to put systems onto an FPGA. Instead, Nexar enables designers to use familiar, board-level design methodologies to interactively design and implement a complete embedded system inside an FPGA, making the potential of FPGA-based embedded systems design accessible to all engineers.