May 10, 2005 -- Verific Design Automation, Inc. today announced that Calypto Design Systems, Inc. has licensed its hardware description language (HDL) Component Software. Verific's HDL Component Software of C++ source code-based parsers, analyzers and elaborators for Verilog and VHDL serves as the standard front-end for Calypto's breakthrough SLEC functional verification software.
According to Calypto, the SLEC product family is the first commercially available sequential verification solution that proves functional equivalence between two IC designs that contain differences in levels of abstraction and sequential behavior. SLEC can compare functionality of designs written in any combination of VHDL, Verilog, SystemC or a C/C++ hardware description.
"The decision to work with Verific was an easy one for us because its HDL Component Software is the standard front-end source code," says Gagan Hasteer, Calypto's vice president of engineering.
