May 16, 2005 -- Azuro, Inc. today announced PowerCentric, a low power clock implementation solution that significantly reduces the power consumption of digital chips. According to the company, the PowerCentric solution differs from existing industry design flows where clock gating and clock tree synthesis are performed at two different points in the flow. By unifying these operations at the placed gates level in the design flow, PowerCentric's patent-pending iCTS technology is able to explore a larger global solution space of clock gating topologies and make power-timing trade-offs that are superior to current industry solutions.

PowerCentric also includes a fully integrated vectorless active power reporting engine, eliminating the need to produce representative power testbenches before power characterizing a design. "You cannot optimize what you cannot accurately measure," explained Steev Wilcox, co-founder and chief architect of Azuro. "Our SASim vectorless power estimation technology enables PowerCentric to implement the best trade-offs and save the most power during optimization."