June 3, 2005 -- Verific Design Automation, Inc. today announced that Renesas Technology Corp. has selected its hardware description language (HDL) Component Software for use in its internal electronic design automation environment.

Verific's ability to support both operations on the parsetree and a fully elaborated netlist from register transfer level (RTL) was an important consideration for Renesas. "This is not an easy requirement," affirms Keiichi Suzuki, senior engineer, System level Design and Verification Technology Dept., LSI Product Technology Unit at Renesas Technology Corp. "Verific's commitment to customer support by the R&D team is commendable. Their dedication ensured that we got the features we needed, and made a significant impact with us."

Renesas develops chips with advanced networking, security, low-power and analog technologies, positioning itself as being at the forefront of ubiquitous networking for mobile technologies, automotive, and PC/audio visual equipment. It purchased source code for Verific's Verilog 2001, VHDL and RTL-to-netlist component software packages, as well as Verific's parsetree software package for its internal development effort. All have been implemented in a state-of-the-art process that makes use of both the netlist and the parsetree.