November 9, 2005 -- Atmel Corp announced today its 0.18µm AT58900 RF CMOS process technology for ASIC foundry customers whose products require high speed, low power RF devices, such as those used in WLAN, WiMAX and ZigBee applications. This new process is manufactured on 200mm wafers and features 1.8V CMOS transistors and an array of passive components that include low tolerance analog poly resistors, N+ and P+ S/D resistors, and up to four metal layers. RF pads are included to help minimize interface impedance.

Optional features include single poly EEPROM for on-chip analog trimming or low density data storage. Minimization of circuit noise can be achieved using optional triple well isolation transistors, low channel-leakage MOS transistors, and isolated NMOS transistors. Other optional features include high Q, low noise metal-insulator-metal capacitors, and P+/N- varactors for optimum linearity. On-chip thick aluminum inductors are available for impedance matching, which reduces off-chip component requirements. Designers have access to fifth and sixth metal layers to help simplify signal routing. A 3.3V I/O interface can be incorporated eliminating the need for off-chip voltage doublers.

Atmel offers frequent multi-project wafer (MPW) runs that provide an economical means for customers to debug prototype RF devices without purchasing an entire mask set. Multiple customers share the same reticle and wafer-run, thereby reducing the cost of entry. Prices for MPW runs are dependent on the die size. Atmel accepts minimum order quantities (MOQ) as low as $250K per year for production foundry products. All backend services including test, characterization, qualification, design verification, and supply chain management are available if required.

Atmel also offers a range of mature design libraries and a Cadence design kit for the AT58900 that supports accurate mixed signal simulation between digital, analog and RF circuits. The digital standard cell libraries are supported in OPUS.

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