June 6, 2006 -- Brion Technologies, Inc. today announced the successful completion of its initial joint development agreement with the Crolles2 Alliance, enabling STMicroelectronics, Philips Semiconductors and Freescale Semiconductor to put Brion’s Tachyon LMC, model-based, full-chip, through-process-window, lithography manufacturability verification solution in production on a fully automated 65-nm process flow.

Based on the success of the joint development work, which began in April 2005, the Crolles2 Alliance has placed a follow-on order for additional Tachyon capacity, including both Tachyon LMC for 65-nm and 45-nm RET verification and Tachyon RDI design inspection for 90nm. The alliance has also entered into a new agreement with Brion to develop OPC for 45-nm devices. The joint development work will use Brion’s Tachyon OPC+, a tool that gives users an accurate and predictable method for creating OPC and RET features without sacrificing speed or cost of ownership.

"Brion’s Tachyon LMC model-based, full-chip verification technology fundamentally changes how we approach production of 65-nm designs," said Joël Hartmann, Operations Director for Crolles2, based in Crolles, France. "Using Tachyon, we achieve faster and more predictable cycle times - accelerating our chip time-to-market."

Both Tachyon LMC and OPC+ use Brion’s Focus Exposure Modeling (FEM) technology, a one-model, through-process-window, full-chip lithography simulation capability that serves as the basis for achieving exceptional accuracy and speed.