October 17, 2006 -- Verific Design Automation, Inc. today announced that Denali Software, Inc. has deployed Verific's hardware description level (HDL) component software for its internal development. Denali licensed Verific's SystemVerilog parser, analyzer and static elaborator to be used within Denali's internal design tool flow. The SystemVerilog software, delivered to Denali as source code, is written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms for both 32- and 64-bit compilers.
"We are happy working with Verific, as utilizing SystemVerilog represents a cornerstone of our configurable IP strategy," says Brian Gardner, Vice President of IP Products at Denali. "Incorporating its tool into our flows saves us valuable time and resources. We find Verific's customer support and service to be exceptional."
