December 4, 2006 -- Novelics, Inc. has announced the availability of its 180-nm and 130-nm coolSRAM-1T products, available in major foundries. A leading provider of multi-standard ASICs for mobile TV and digital audio broadcast standards started production ramp-up of chips with the Novelics embedded coolSRAM-1T.

SOC designers successfully used Novelics' differentiated memory IPs such as coolSRAM-1T, and worked with Novelics' engineering and management team, to maximize the value of their industry-leading ICs in designs with over 256kbits of embedded memory. For example, the mobile TV customer's SOC can support standards, including DVB-H, DMB, ISDB-T and FLO. The company is currently demonstrating its silicon operating without any external memory.

"Our target customers compete in low power consumer, video multimedia processors, HDTV, gaming, wireless applications, LCD controller, printer engines, high speed computing and networking," said Farzad Zarrinfar, President of Novelics. "We are excited that fabless semiconductor companies who have leading solutions in explosive markets such as 'TV-enabled cellular phones' have chosen our technology."

coolSRAM-1T is supported in TSMC's 180-nm, 130-nm and 90-nm process nodes, in UMC's 130-nm and 90-nm nodes, SMIC's 90-nm, and in Silterra's 180-nm and 130-nm nodes. coolSRAM-1T is implemented with standard logic CMOS process with no additional masks or process steps, thus minimizing implementation costs, as well as maximizing reliability and portability.

Low power

The coolSRAM-1T memory array has been designed for ultra-low power consumption through a combination of techniques to lower active power and leakage power dissipation. The coolSRAM-1T does not dissipate any static DC current other than the junction and sub-threshold leakage inherent in any circuit.

coolSRAM-1T supports active standby and sleep modes. During sleep mode, the clock and a large percentage of the circuits are suppressed to drastically reduce power dissipation. During standby mode, the memory retains data by using a low frequency refresh operation that dissipates minimal power. The overall architecture and circuits used in coolSRAM-1T design result in both low active and low leakage power dissipations. Internal refresh logic is provided as part of the memory array that can transparently provide the refresh, or designers can select an external refresh option if they want to control the refresh externally.

Memory compiler

A key enabling technology for coolSRAM-1T is Novelics' MemQuest memory compiler. This tool lets designers configure the lowest power, fastest or most dense coolSRAM-1T with the same compiler, thus eliminating potential non-recurring engineering fees for manual implementation. The compiler also lets designers use the most optimum core size with the shortest time to market. MemQuest is based on fully-customized and hand-crafted memory sub-circuits and leaf cells. Therefore, it generates results that are typically within 5% of full custom designs and eliminates manual work in generating memory instances. As a result, the MemQuest compiler provides a higher figure of merit (power/speed/density concurrency) than other options.

The coolSRAM-1T core memory cell employs a transistor and a structural capacitor to implement the storage cell. In comparison with traditional SRAM, fewer transistors are needed in each cell and thus memory arrays built with coolSRAM-1T cells can achieve a 2X reduction in core size vs. arrays based on standard six-transistor memory cells.