December 18, 2006 --In a survey of Design Automation Conference (DAC) attendees taken during the conference in July, EVE found that 60% of respondents were satisfied with their current verification environment. EVE, known for its ZeBu (Zero Bugs) hardware-assisted verification platform, conducted this survey to better understand electronics design trends and what tools are needed to make design teams more effective. Of 617 surveys collected during the four-day conference, 477 were used to compile the survey.

Among the findings, close to 60% of respondents said that their design team performed hardware/ software co-verification, and 55% use or plan to use hardware-assisted verification. The survey showed trends toward bigger designs (72% noted that their designers were larger than two million gates) and a growing need for better performance or software development, leading to a strong desire for hardware-assisted verification solutions.

"This survey has been incredibly useful," says Lauro Rizzatti, general manager of EVE-USA. "It confirmed our theory that only companies offering fast solutions at a low price with a decent setup time, automated compilation flow and hardware debugging will thrive. The others will stagnate in the emulation market or be replaced by newcomers in the prototyping market where it is well known that the barriers to entry are quite low."

Other findings

Assertion-based design is used by 49% of respondents in the verification flow, with cycle-based simulation weighing in at 27% and transaction-based verification at 24%.

As for hardware/software co-design, 31% of respondents are using emulation, 29% employ FPGA prototyping, 15% have chosen virtual prototyping, 13% use electronic system level (ESL) tools and 12% are working with instruction set simulation (ISS).

Respondents included front- and back-end designers, front- and back-end verification engineers and system designers. Other respondents listed their job functions as EDA management, software engineers, sales and marketing. They are designers of ASICs (42%), SOCs (26%), intellectual property (IP) (13%) and custom ICs (12%).

Applications ranged from consumer electronics (23%) and communications and wireless (16% each), processor (11%), followed by networking, computers and peripherals, multimedia, military/defense electronics, aerospace and Homeland Security, all under 10% of respondents.

The largest percentage of respondents noted that their chips were less than two-million gates (28%), while 25% wrote that their chips were in the two- to five-million gate range. Others said that their designs were in the five- to 10-million gate range (22%), 15% wrote that their designs ranged from 10-50 million gates and 10% said that their chips were larger than 50-million gates.

While most respondents listed execution speed as needing the most improvement in the verification environment, ease of use, setup and compile speed also need improvement, as does coverage, price and reusability.

Within the verification flow, the survey found that 25% of respondents believe that block-level testing needs the most improvement, followed by software integration at 19%. Hardware regression testing and block-level regression testing weighed in at 18% and 17%, respectively. Other areas that need improvement include software applications, software drivers and graphical user interface (GUI)/utilities development, and real-time operating systems (RTOS).