April 23, 2007 -- Coupling Wave Solutions (CWS) today introduced WaveIntegrity, a software platform to model electrical signal integrity (ESI), or the noise generated and propagated through the IC's substrate, interconnect and package. WaveIntegrity offers a complete solution to assess the design margin of noise in analog and radio frequency (RF) functions integrated in complex system-on-chips (SoCs) and system in packages (SiPs). According to CWS, this platform is the first tool suite designed to help intellectual property (IP) block authors and system integrators effectively incorporate analog and RF blocks in SoC or SiP designs.

The four individual tools in WaveIntegrity share a common set of extraction and analysis engines that allow the computation of the system-level noise injected by all blocks. Propagation is evaluated through a combination of substrate, interconnect and package magneto-static parasitics. Propagated noise can be monitored at any point in the system — from power supply nodes to a specific location at the surface of the silicon substrate. The corresponding waveform or spectral distribution is stored for later visualization or inclusion during detailed functional simulation.

In addition, for each monitored node, WaveIntegrity lists major aggressors and their relative contribution to noise. This, together with the ability to extract specific transfer functions between an aggressor and its target, offers an effective way to fix all ESI issues in systems integrating analog and RF blocks.

The WaveIntegrity platform is the result of a close partnership with industrial leaders such as NXP Semiconductors and STMicroelectronics. Marcel Pelgrom, Senior Fellow at NXP Research, observes: "NXP recognizes the importance of comprehensive noise analysis combining substrate, interconnect and package parasitics for our advanced consumer and communication SOCs. The blend of experimental evidence in 90- and 65-nanometer CMOS and circuit knowledge at NXP, together with CWS' expertise in tools and algorithmic know-how, results in an excellent cooperation in assessing the potential of the CWS tools for these applications."

Didier Belot, Analog RF Design senior expert from STMicroelectronics, notes: "Enabling higher levels of integration complexity by evaluating and addressing key RF and analog signal integrity issues is absolutely critical for STMicroelectronics. During our partnership, CWS has proven that it has a unique expertise for addressing complex mixed analog RF CMOS SOCs with more than one-million transistors, either in 130-nm or in 65-nm with frequencies up to 10GHz. The tool suite has been evaluated for the sign-off on one circuit and is used presently for the design support in another application. Both cases have been successful."

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