March 24, 2008 -- Calypto Design Systems, Inc. today announced immediate availability of PowerPro CG 2.0, featuring new sequential clock-gating optimizations that extend its power savings capability to a wider range of design applications in storage and processor markets. In addition, the 2.0 release includes PowerPro Analyzer, a graphical visualization tool with hyperlinked source code, schematics and clock-gating views that enable users to rapidly navigate and analyze power optimizations.

PowerPro CG is an automated register transfer level (RTL) power-optimization product that reduces power consumption in typical system-on-chip (SOC) devices by 10% to 60% with little or no impact on timing or area. It delivers consistently better results in significantly less time than the error-prone and time-consuming manual techniques currently used by designers.

PowerPro CG uses Calypto’s patented sequential analysis technology to evaluate circuit behavior across multiple clock cycles and identify sequential clock gating logic to reduce dynamic power. PowerPro CG then inserts this logic into the user’s original synthesizable RTL code, while maintaining all of the original RTL constructs including any existing pragmas and comments. Compared to combinational clock gating, sequential clock gating saves more power by turning off a larger number registers for longer durations.

New sequential clock gating optimizations in PowerPro CG 2.0 exploit the type of control and data interactions typically found in storage and processor designs. PowerPro CG 2.0 is easily integrated into low-power RTL synthesis design flows. Calypto’s SLEC (Sequential Logic Equivalence Checker) product is integrated with PowerPro CG to comprehensively verify sequential clock-gating optimizations.

Pricing and Availability