January 23, 2009 -- Calypto Design Systems, Inc. is collaborating with ARC International to reduce power in ARC’s low-power video subsystem intellectual property (IP) solution using Calypto’s PowerPro CG. ARC’s video subsystems are ideal for applications such as high-end cell phones, digital video recorders, webcams, and portable media players to provide encoding and/or decoding functionality.
"Enabling our customers to build unique, low-power solutions with our multimedia subsystems is a first-order priority," remarks Paul Holt, ARC’s Vice President, SoC Business Unit. "PowerPro CG’s ability to further reduce power in our IP offering will be beneficial to our users, many of whom are tasked with meeting ever-shrinking power budgets in portable devices.”
Calypto’s PowerPro CG is an automated register transfer level (RTL) power-optimization tool that inserts advanced sequential clock gating structures into an RTL design and is proven to reduce power by up to 60% on customer designs.
PowerPro CG was able to significantly reduce power on ARC’s AV401 video subsystem in a high-performance H.264 application, translating into a measured power savings of 15% in this particular design operating at 200MHz. The ARC AV401 is a user-configurable video decoding platform that provides video decoding for multiple standards to allow playback of virtually any content. While the AV401 is already a low-power video decode platform, PowerPro CG was applied to the design of the video codec, showcasing how PowerPro CG can be applied by a user to ARC’s configurable IP block to further reduce power for a variety of video applications.
PowerPro CG reads in a synthesizable RTL design and generates a new RTL design which is an identical to the original design with additional clock-gating enable logic. The low-power RTL is then comprehensively verified using sequential logic equivalence checking to ensure no functional changes are introduced.
Go to the Calypto Design Systems, Inc. website to find additional information.
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