February 9, 2004 -- Verific Design Automation, Inc. today said that its products now support Accellera's property specification language (PSL)/Sugar. This means that all of its hardware design language (HDL) component software packages now include a PSL/Sugar reader, and will enable assertion-based verification.

"The PSL/Sugar Consortium is pleased that Verific is offering assertion-based specifications within its HDL component software packages," says Harry Foster, the consortium's formal verification technical committee chair. "This allows EDA companies to swiftly introduce native PSL/Sugar support in their verification tools. We were waiting for something like this to happen."

In addition, Verific has joined the PSL/Sugar Consortium, an organization intent on helping hardware designers adopt and implement PSL/Sugar and its methodologies to speed system-level design and verification. PSL/Sugar, based on the IBM Sugar assertion language, is a powerful, concise language for assertion specification and complex modeling. It provides an interoperable specification language to exchange hardware specifications and develop seamless tool integration.

"PSL/Sugar is helping meet the demands of complex chip design," says Rob Dekker, president of Verific. "We believe in supporting standards and PSL/Sugar is a comprehensive standard which will fully enable assertion-based verification for Verilog, VHDL and mixed-language designs. That's why we've added it to our growing list of products and joined the PSL/Sugar Consortium."

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