Page loading . . .

  
 You are at: The item(s) you requested.Friday, September 03, 2010
NEC Selects Verific Design Automation HDL Component Software  
 Printer friendly
 E-Mail Item URL

June 2, 2004 -- NEC's System Devices Research Laboratories has purchased a license for Verific Design Automation, Inc.'s HDL Component Software.

"NEC spends significant resources in advancing state-of-the-art EDA research to maintain its leadership position in SOC design," says Dr. Masao Fukuma, vice president and general manager of NEC System Devices Research Laboratories. "Using Verific's software fits right into our best-in-class strategy."

NEC enhances the capability of its C-based system-on-chip (SOC) design environment where Verific's VHDL, Verilog 2001 and other related software will act as a front-end for NEC's (SOC) design environment. NEC received source code for VHDL and Verilog parsers, analyzers, and elaborators, as well as an RTL database. The Verific software is written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms.

"We very much liked that Verific provides us with source code," adds Dr. Katsuharu Suzuki, NEC's technical lead. "In addition, support and training so far have been excellent."

Go to the Verific Design Automation, Inc. website to find additional information.
 Please click here to let us know if the above link is broken!

E-mail Verific Design Automation, Inc. for more information.

Read more about
Verific Design Automation, Inc.
on SOCcentral.com


Keywords: Verific Design Automation,
550/6807 6/2/2004 2256 403
Designer's Mall
0.375



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Tips

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Seeing Is Believing: How Visualization Simplifies IC DRC


Michael White
Senior Product Marketing Manager
Mentor Graphics Corp.

Tech Viewpoint

Verification Challenges
Require
Surgical Precision


Dr. Pranav Ashar
Chief Technical Officer
Real Intent, Inc.

Odd Parity

Summertime and the
Leavin’ Ain’t Easy


Mike Donlin
The Write Solution

Odd Parity Archive

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Design for Manufacturing
Design for Test
ESL Design
Floorplanning & Layout
Formal Verification
Logic & Physical Synthesis
Low-Power Design
On-Chip Interconnect
Reconfigurable Computing
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
.
Designer's Kiosk
Whitepapers & App Notes
Live and Archived Webcasts


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2010  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.453125