SOCcentral | |
|
Table of Contents |
| The Front Page |
| About SOCcentral |
| EDA/EDA Tools: Compilers: |
csrCompiler (Semifore, Inc.) |
MegaCell Compiler (MCC) (Micro Magic, Inc.) |
SystemC to VHDL/Verilog Compiler (Prosilog SA) |
VHDL to SystemC Compiler (Prosilog SA) |
| EDA/EDA Tools: Design Entry: |
Allegro Design Entry CIS 210 (Cadence Design Systems, Inc.) |
Filter Wiz (Schematica Software) |
Gateway Schematic Editor (Simucad Design Automation, Inc.) |
MAX-View Layout Viewer (Micro Magic, Inc.) |
Pillar-DP: Physical Effect Aware Specification Validation (Entasys Design, Inc.) |
SUE Design Manager (Micro Magic, Inc.) |
Virtuoso Layout Editor (Cadence Design Systems, Inc.) |
| EDA/EDA Tools: Design for Manufacture: |
AMPSO-OADFM: Optimization Tool of Analog Design for Manufacturability (Anasift Technology, Inc.) |
ChampiAn: CMP Process Analysis and Characterization (UbiTech, Inc.) |
ChampiIDF: Intelligent Model-based Dummy Filler (UbiTech, Inc.) |
Champisim-Cu: Chip-scale Cu CMP Profile Simulator (UbiTech, Inc.) |
DesignMD (ChipMD, Inc.) |
Paramos (Synopsys, Inc.) |
PASCAL: 2D/3D R, L, C Simulator (UbiTech, Inc.) |
ROAD Suite Statistical Optimizer and Analyzer (Extreme DA) |
ScanWorks Manufacturing Station (ASSET InterTech, Inc.) |
Seismos (Synopsys, Inc.) |
| EDA/EDA Tools: Design for Test: |
BSD Compiler (Synopsys, Inc.) |
DFT Analyzer (ASSET InterTech, Inc.) |
DFT-PRO Plus (SynTest Technologies, Inc. ) |
Encounter Test Solutions (Cadence Design Systems, Inc.) |
FlopPlot Scan Diagnostic Data Management and Analysis Tool (Inovys Corp.) |
Ocelot ATE (Inovys Corp.) |
Personal Ocelot Desktop Test System (Inovys Corp.) |
ScanWorks Diagnostic & Repair Station (ASSET InterTech, Inc.) |
ScanWorks JTAG Programming Stations (ASSET InterTech, Inc.) |
ScanWorks Test Development Station (ASSET InterTech, Inc.) |
TetraMAX ATPG (Synopsys, Inc.) |
TurboBIST-Logic (SynTest Technologies, Inc. ) |
TurboBIST-Memory (SynTest Technologies, Inc. ) |
TurboBSD Boundary Scan Designer (SynTest Technologies, Inc. ) |
TurboCheck Testability Analysis (SynTest Technologies, Inc. ) |
TurboDebug-PCB Debug System for Interconnect Faults (SynTest Technologies, Inc. ) |
TurboDFT DFT Integration Tool Suite (SynTest Technologies, Inc. ) |
TurboFault Fault Simulation (SynTest Technologies, Inc. ) |
TurboScan Scan Synthesis and ATPG (SynTest Technologies, Inc. ) |
VirtualScan Tool Suite for Virtual Scan Synthesis and ATPG (SynTest Technologies, Inc. ) |
| EDA/EDA Tools: Design Management: |
6thGear Collaboration Optimizer (InterWeave Tech Corp.) |
Allegro Design Entry HDL 610 (Cadence Design Systems, Inc.) |
Cadence and TSMC Library Distribution (Cadence Design Systems, Inc.) |
Chameleon (Cadence Design Systems, Inc.) |
Diva Physical Verification (Cadence Design Systems, Inc.) |
Encounter digital IC design platform (Cadence Design Systems, Inc.) |
Incisive Conformal Ultra (Cadence Design Systems, Inc.) |
SOS (ClioSoft, Inc.) |
SOS viaDFII (ClioSoft, Inc.) |
VN-Spec Requirement Traceability and Impact Analysis (TransEDA) |
| EDA/EDA Tools: Design Suites: |
1Team:Implement (Atrenta, Inc.) |
Analog Office Design Suite for Analog and RFIC Design (Applied Wave Research, Inc. (AWR)) |
Assura Design Rule Checker (Cadence Design Systems, Inc.) |
CoDesign Studio (Sigrity, Inc.) |
GoldTime Sign-off Suite (Extreme DA) |
L-Edit Pro (Tanner EDA) |
LINMIC 6.1 Microwave & RF IC Design Suite (AC Microwave GmbH) |
Magillem Graphical Platform Builder for SoCs (Prosilog SA) |
Microwave Office Design Suite (Applied Wave Research, Inc. (AWR)) |
Nepsys IP Design and Verification Environment (Prosilog SA) |
TestWave (Applied Wave Research, Inc. (AWR)) |
Visual System Simulator Design Suite (Applied Wave Research, Inc. (AWR)) |
| EDA/EDA Tools: Development Kits: |
2D Fabric Evaluation and Demo Board (Xilinx, Inc.) |
Celoxica/SBS Tsunami FPGA Processor Development Kit (Celoxica, Ltd.) |
CPU + FPGA (Virtex/Spartan-II) MicroEngine Cards (Xilinx, Inc.) (Intrinsyc Software, Inc.) |
CPU + FPGA (Virtex-II) MicroEngine Cards (Xilinx, Inc.) (Intrinsyc Software, Inc.) |
HSA - Wireless/High Speed Analog I/O Module (Xilinx, Inc.) |
HSA - Wireless/High Speed Analog I/O Module (Xilinx, Inc.) |
LogiCRAFT Evaluation System (Xilinx, Inc.) (Xylon) |
NanoBoard (Altium, Ltd.) |
PF3100 PC/104-Plus Reconfigurable Module (Xilinx, Inc.) (Derivation Systems, Inc.) |
Platform Developer's Package (Celoxica, Ltd.) |
RC2000 Development Board (Celoxica, Ltd.) |
RC203 Development Board (Celoxica, Ltd.) |
RC300 High Performance Development and Evaluation Board (Celoxica, Ltd.) |
| EDA/EDA Tools: DSP Tools: |
3DSP Software Studio (3DSP Corp.) |
AccelWare DSP IP Core Generators (AccelChip, Inc.) |
DSP synthesis with IP-Explorer Technology (AccelChip, Inc.) |
HiFi DSP Configuration Tool (3DSP Corp.) |
Sketchpad Development Kit (3DSP Corp.) |
Synplify DSP (Synplicity, Inc.) |
| EDA/EDA Tools: ESL Tools: |
DK Accelerator for Altera SOPC Builder (Celoxica, Ltd.) |
DK Design Suite (Celoxica, Ltd.) |
DK Design Suite for Xilinx EDK (Celoxica, Ltd.) |
eXCite Professional/ FPGA (Y Explorations, Inc. (XYI)) |
Panorama VPD (Summit Design, Inc.) |
Vista Integrated Developement and Verification Environment for SystemC (Summit Design, Inc.) |
Vista Personal Edition (Vista-PE) for SystemC (Summit Design, Inc.) |
Visual Elite System Design (Summit Design, Inc.) |
| EDA/EDA Tools: FPGA/CPLD/PLD Tools: |
Binachip-FPGA (Binachip, Inc.) |
Designer FPGA Development Software (Actel Corp.) |
Libero Integrated Design Environment (IDE) (Actel Corp.) |
| EDA/EDA Tools: PCB/MCM Tools: Design Entry: |
Allegro PCB Design 220 (Cadence Design Systems, Inc.) |
Allegro PCB Design 610 (Cadence Design Systems, Inc.) |
Allegro PCB Librarian (Cadence Design Systems, Inc.) |
| EDA/EDA Tools: PCB/MCM Tools: Placement & Routing: |
Allegro PCB Router (Cadence Design Systems, Inc.) |
NanoRoute Ultra (Cadence Design Systems, Inc.) |
| EDA/EDA Tools: PCB/MCM Tools: Signal Integrity: |
Allegro PCB SI (Cadence Design Systems, Inc.) |
Broadband SPICE (Sigrity, Inc.) |
CeltIC (Cadence Design Systems, Inc.) |
PowerSI (Sigrity, Inc.) |
SIwave Analysis for Signal Integrity and Power Delivery (Ansoft Corp.) |
SPEED2000 (Sigrity, Inc.) |
XcitePI (Sigrity, Inc.) |
| EDA/EDA Tools: Physical Design: |
Allegro Package SI 620 (Cadence Design Systems, Inc.) |
| EDA/EDA Tools: Physical Design: Characterization: |
AccuCell Characterization and Modeling Tool (Simucad Design Automation, Inc.) |
AccuCore Block Characterization and Analysis (Simucad Design Automation, Inc.) |
Creative Genius (Analog Design Automation, Inc.) |
EXACT Interconnect Parasitic Characterization (Simucad Design Automation, Inc.) |
IP Explorer (Analog Design Automation, Inc.) |
MemChar Memory Characterization Tool (Legend Design Technology, Inc.) |
PLL Noise Analyzer (Berkeley Design Automation, Inc.) |
SpiceCut Memory (Legend Design Technology, Inc.) |
| EDA/EDA Tools: Physical Design: DRC/ERC/LVS: |
Guardian DRC/LVS/LPE Physical Verification (Simucad Design Automation, Inc.) |
HiPer Verify DRC Engine (Tanner EDA) |
| EDA/EDA Tools: Physical Design: HDL Translators: |
verilog2vhdl (Alternative System Concepts, Inc.) |
VHDL2verilog (Alternative System Concepts, Inc.) |
| EDA/EDA Tools: Physical Design: Layout/Floorplanning: |
Expert Layout Editor (Simucad Design Automation, Inc.) |
Fire & Ice QXC (Cadence Design Systems, Inc.) |
GTmerge (XYALIS) |
GTmuch Multi Chip Project Editor (XYALIS) |
GTsmooth (XYALIS) |
GTsuite (XYALIS) |
GTtiler (XYALIS) |
GTviewer (XYALIS) |
Laker L2 (Silicon Canvas, Inc.) |
Laker L3 (Silicon Canvas, Inc.) |
MAX/MAX-LS Intelligent Layout Environments (Micro Magic, Inc.) |
| EDA/EDA Tools: Physical Design: Modeling/Libraries: |
Fire & Ice QXT (Cadence Design Systems, Inc.) |
MaskCompose (Cadence Design Systems, Inc.) |
Variety Library Generator (Altos Design Automation, Inc.) |
| EDA/EDA Tools: Physical Design: Parasitic Extraction: |
Assura Parasitic Extraction (RCX) (Cadence Design Systems, Inc.) |
CLEVER Physics-Based Parasitic Extractor (Simucad Design Automation, Inc.) |
Columbus-RF (Sequence Design, Inc.) |
Columbus-Turbo (Sequence Design, Inc.) |
ExtractionStage (Sequence Design, Inc.) |
HIPEX Full-Chip Parasitic Extraction (Simucad Design Automation, Inc.) |
Pillar-PNA: Power Network Analysis (Entasys Design, Inc.) |
QUEST High Frequency Parasitic Extraction (Simucad Design Automation, Inc.) |
QuickCap (Magma Design Automation, Inc.) |
STELLAR Standard Cell Parasitic Characterization (Simucad Design Automation, Inc.) |
| EDA/EDA Tools: Physical Design: Placement & Routing: |
Analog Layout Integrated Synthesis (SynCira Corp.) |
Companion (Sagantec, Inc.) |
Hurricane (Sagantec, Inc.) |
Nano Encounter (Cadence Design Systems, Inc.) |
NexusRoute (Pyxis Technology, Inc.) |
SiClone (Sagantec, Inc.) |
SiFix (Sagantec, Inc.) |
XTREME (Sagantec, Inc.) |
| EDA/EDA Tools: Physical Design: Power Analysis: |
Blast Rail (Magma Design Automation, Inc.) |
CoolTime (Sequence Design, Inc.) |
Power Optimize Gold (Golden Gate Technology, Inc.) |
Power Plan Gold (Golden Gate Technology, Inc.) |
PowerDC (Sigrity, Inc.) |
PowerTheater (Sequence Design, Inc.) |
PowerTheater Analyst (Sequence Design, Inc.) |
PowerTheater Designer (Sequence Design, Inc.) |
PrimeRail (Synopsys, Inc.) |
RedHawk (Apache Design Solutions, Inc.) |
SkyHawk (Apache Design Solutions, Inc.) |
| EDA/EDA Tools: Physical Design: Signal Integrity: |
Blast Noise (Magma Design Automation, Inc.) |
Diamond SI (Magma Design Automation, Inc.) |
SiAuditor (Signal Integrity Software, Inc. (SiSoft)) |
| EDA/EDA Tools: Physical Design: Timing Analysis: |
Blast Fusion netlist-to-GDSII chip implementation system (Magma Design Automation, Inc.) |
Blast Logic (Magma Design Automation, Inc.) |
Blast Plan (Magma Design Automation, Inc.) |
CRITIC Timing Analyzer for Cell-Based Designs (Nassda Corp.) |
HANEX Timing Analyzer for Nanometer Custom Designs (Nassda Corp.) |
PhysicalStudio (Sequence Design, Inc.) |
PsiWinder (Apache Design Solutions, Inc.) |
ShowTime (Sequence Design, Inc.) |
| EDA/EDA Tools: Prototyping/Emulation: |
Certify ASIC (Synplicity, Inc.) |
Design Pilot (Aptix Corp.) |
Explorer Software (Aptix Corp.) |
First Encounter Ultra (Cadence Design Systems, Inc.) |
Logic AggreGATEr (Aptix Corp.) |
Prototype Studio/Enterprise (Aptix Corp.) |
Prototype Studio/PCB (Aptix Corp.) |
Prototype Studio/Pro (Aptix Corp.) |
Software Integration Station (SIS) (Aptix Corp.) |
Synplify Proto (Synplicity, Inc.) |
System Explorer MP3C (Aptix Corp.) |
System Explorer MP4C (Aptix Corp.) |
ZeBu (Emulation and Verification Engineering (EVE)) |
| EDA/EDA Tools: Simulation: Acceleration: |
Incisive Conformal ASIC (Cadence Design Systems, Inc.) |
Incisive Unified Simulator (Cadence Design Systems, Inc.) |
Incisive XLD (Cadence Design Systems, Inc.) |
Incisive XLD Base (Cadence Design Systems, Inc.) |
| EDA/EDA Tools: Simulation: Analog/Mixed Signal: |
GoldenGate RFIC Simulator (Xpedion Design Systems, Inc.) |
Harmony Analog/Mixed-Signal Simulator (Simucad Design Automation, Inc.) |
Incisive AMS (Cadence Design Systems, Inc.) |
| EDA/EDA Tools: Simulation: Circuit Simulation: |
AASPICE: Analog SPICE Simulator (Anasift Technology, Inc.) |
AMPSO: High Performance Analog Optimization Tool (Anasift Technology, Inc.) |
Dracula Verification (Cadence Design Systems, Inc.) |
eScetch Circuit Simulation Software (Schematica Software) |
HSIM Hierarchical Circuit Simulation and Analysis Tool (Nassda Corp.) |
LEXSIM Full-Chip Post-Layout Circuit Simulation Tool (Nassda Corp.) |
MDSPICE: Mixed-Domain SPICE Simulator (Zeland Software, Inc.) |
MSIM Characterization-Oriented Circuit Simulator (Legend Design Technology, Inc.) |
NSPICE (HSPICE Compatible Simulator) (Apache Design Solutions, Inc.) |
SmartSpice Analog Circuit Simulator (Simucad Design Automation, Inc.) |
SPAYN Statistical Parameter and Yield Analysis (Simucad Design Automation, Inc.) |
SpiceVision (Concept Engineering GmbH) |
T-Spice Pro (Tanner EDA) |
UTMOST III SPICE Modeling Software (Simucad Design Automation, Inc.) |
| EDA/EDA Tools: Simulation: EM Simulation: |
3D Electromagnetic COAX Simulator for Coaxial Structures (AC Microwave GmbH) |
Ansoft Designer (Ansoft Corp.) |
ePhysics Coupled Thermal & Stress Analysis for EM Applications (Ansoft Corp.) |
Fidelity: FDTD-Based EM Simulator (Zeland Software, Inc.) |
HFSS: 3D EM Simulation Software for RF, Wireless, Packaging Design (Ansoft Corp.) |
IE3D: MoM-Based EM Simulator (Zeland Software, Inc.) |
LINMIC Interconnect (AC Microwave GmbH) |
| EDA/EDA Tools: Simulation: Fault Simulation: |
HyperFault Mixed-Level Fault Simulator (Simucad Design Automation, Inc.) |
| EDA/EDA Tools: Simulation: Functional Simulation: |
System Architect (Summit Design, Inc.) |
| EDA/EDA Tools: Simulation: Mixed Verilog/VHDL: |
Active-HDL (Aldec, Inc.) |
Riviera (Aldec, Inc.) |
Riviera IPT (Aldec, Inc.) |
| EDA/EDA Tools: Simulation: RF Circuit Simulation: |
SmartSpiceRF Harmonic Balance Based Simulator (Simucad Design Automation, Inc.) |
| EDA/EDA Tools: Simulation: Verilog: |
SILOS Verilog Simulator (Simucad Design Automation, Inc.) |
| EDA/EDA Tools: Synthesis: |
BuildGates (Cadence Design Systems, Inc.) |
Encounter RTL Compiler (Cadence Design Systems, Inc.) |
| EDA/EDA Tools: Synthesis: Analog Synthesis: |
Analog Silicon Implementation (Accelicon Technologies, Inc.) |
COCAFIL: Waveguide Filter Design Suite (Zeland Software, Inc.) |
FilterSyn (Zeland Software, Inc.) |
| EDA/EDA Tools: Synthesis: ASIC Synthesis: |
Amplify ASIC Physical Optimizer (Synplicity, Inc.) |
Amplify ISSP (Synplicity, Inc.) |
Amplify RapidChip (Synplicity, Inc.) |
Blast Create (Magma Design Automation, Inc.) |
Blast RTL (Magma Design Automation, Inc.) |
Synplify ASIC (Synplicity, Inc.) |
| EDA/EDA Tools: Synthesis: FPGA/CPLD Synthesis: |
Agility Compiler for SystemC Synthesis (Celoxica, Ltd.) |
Aldec Mixed RTL/C Package with Celoxica DK (Celoxica, Ltd.) |
Amplify FPGA Physical Optimizer (Synplicity, Inc.) |
ArchEvaluator - Programmable Architecture Evaluation Product (Magma Design Automation, Inc.) |
Nexus-PDK (Celoxica, Ltd.) |
PALACE (Magma Design Automation, Inc.) |
Synplify Pro (Synplicity, Inc.) |
| EDA/EDA Tools: Uncategorized: |
Accusim II (Mentor Graphics Corp.) |
ADiT – Analog-Digital Turbo simulator (EverCAD Corp.) |
ADM Line Cards (Agere Systems, Inc.) |
ADVance MS (ADMS) (Mentor Graphics Corp.) |
Allegro AMS Simulator 210 (Cadence Design Systems, Inc.) |
Allegro Package Designer 620 (Cadence Design Systems, Inc.) |
AMBA Navigator Logic Analyzer (First Silicon Solutions, Inc. (FS2)) |
Anaconda (Sagantec, Inc.) |
Analog Designer (Mentor Graphics Corp.) |
Analog Virtual Prototyping (Accelicon Technologies, Inc.) |
ANSI C Code Generator (Elanix, Inc.) |
APG Acceleration Option (Elanix, Inc.) |
Apsim DELTA-I (Applied Simulation Technology, Inc.) |
APSIM FDTD (Applied Simulation Technology, Inc.) |
Apsim FDTD-SPAR (Applied Simulation Technology, Inc.) |
APSIM FDTD-SPICE (Applied Simulation Technology, Inc.) |
APSIM IBIS-LCR (Applied Simulation Technology, Inc.) |
Apsim LCD (Applied Simulation Technology, Inc.) |
Apsim Omni (Applied Simulation Technology, Inc.) |
Apsim RADIA (Applied Simulation Technology, Inc.) |
Apsim RADIA-WB (Applied Simulation Technology, Inc.) |
Apsim RLGC (Applied Simulation Technology, Inc.) |
APSIM RPATH (Applied Simulation Technology, Inc.) |
Apsim SI - IC (Applied Simulation Technology, Inc.) |
Apsim SI - PCB (Applied Simulation Technology, Inc.) |
Apsim SPICE (Applied Simulation Technology, Inc.) |
ApsimIBIS-Toolkit (Applied Simulation Technology, Inc.) |
ApsimLPG (Applied Simulation Technology, Inc.) |
Arana (Orora Design Technologies, Inc.) |
ARC Processors (ARC International) |
ARCangel (ARC International) |
ARChitect Processor-Configuration Tool (ARC International) |
Arsyn (Orora Design Technologies, Inc.) |
ASL 1000 (Credence Systems Corp.) |
ASL 3000 (Credence Systems Corp.) |
ASL 3000RF (Credence Systems Corp.) |
Astro (Synopsys, Inc.) |
Astro-Rail (Synopsys, Inc.) |
Aurora (Synopsys, Inc.) |
Avionics Test (Aeroflex Microelectronic Systems) |
Bioinformatics Toolbox (The MathWorks, Inc.) |
Board Architect (Mentor Graphics Corp.) |
Board Station (Mentor Graphics Corp.) |
Board Station RE (Mentor Graphics Corp.) |
BSDArchitect (Mentor Graphics Corp.) |
BUS-AN (OEA International, Inc.) |
Cadabra (Synopsys, Inc.) |
Calibre Interactive (Mentor Graphics Corp.) |
Calibre Mask Data Preparation (Mentor Graphics Corp.) |
Calibre OPC and PSM (Mentor Graphics Corp.) |
Calibre xRC (Mentor Graphics Corp.) |
Calibre xRC-CB (Mentor Graphics Corp.) |
Capital Analysis (Mentor Graphics Corp.) |
Capital Archive (Mentor Graphics Corp.) |
Capital Autoloader (Mentor Graphics Corp.) |
Capital Bridges for Capital Manufacture (Mentor Graphics Corp.) |
Capital Formboard (Mentor Graphics Corp.) |
Capital Harness Systems (Mentor Graphics Corp.) |
Capital Harness Systems - OEM Modules (Mentor Graphics Corp.) |
Capital Integrator (Mentor Graphics Corp.) |
Capital Logic (Mentor Graphics Corp.) |
Capital Manager (Mentor Graphics Corp.) |
Capital Modular (Mentor Graphics Corp.) |
Cascade (CriticalBlue) |
CAT/TransCable Interface (Mentor Graphics Corp.) |
CATS (Synopsys, Inc.) |
CDMA Reference Blockset (The MathWorks, Inc.) |
CelaroPRO Hardware Emulator (Mentor Graphics Corp.) |
CELL-AN (OEA International, Inc.) |
CharFlo-PLL! (Legend Design Technology, Inc.) |
Chess/Checkers (Target Compiler Technologies NV) |
Chipsizer Online Design Tool (UMC (United Microelectronics Corp.)) |
ChipView (Sandwork Design, Inc.) |
Circuit Explorer (Synopsys, Inc.) |
Clock Analysis (Manhattan Routing, Inc. (MRI)) |
CLOCK Designer (OEA International, Inc.) |
Code Composer Studio (Elanix, Inc.) |
CodeWarrior Development Studio (ARC International) |
Communications Toolbox (The MathWorks, Inc.) |
Complete Power Router (Manhattan Routing, Inc. (MRI)) |
Configurable Logic Analyzer Module for Programmable Logic (First Silicon Solutions, Inc. (FS2)) |
CosmosLE (Synopsys, Inc.) |
CosmosScope (Synopsys, Inc.) |
CosmosSE (Synopsys, Inc.) |
CR-5000 Library Tools (Zuken, Ltd.) |
CSG Multi-Carrier Generator (Aeroflex Microelectronic Systems) |
Data Acquisition Toolbox (The MathWorks, Inc.) |
Data Management System (Mentor Graphics Corp.) |
Databahn (Denali Software, Inc.) |
DataFusion (Mentor Graphics Corp.) |
DC Analyzer (Mentor Graphics Corp.) |
DC Ultra (Synopsys, Inc.) |
Debug Detective (Mentor Graphics Corp.) |
Design Architect-IC (Mentor Graphics Corp.) |
Design Compiler (Synopsys, Inc.) |
Design Compiler FPGA (Synopsys, Inc.) |
DesignerSI (Ansoft Corp.) |
DesignView (Mentor Graphics Corp.) |
DesignWare Intellectual Property (Synopsys, Inc.) |
DFTInsight (Mentor Graphics Corp.) |
Diffusion programmable ROM - 0.6/0.5 um (Dolphin Integration) |
Diffusion programmable ROM - 0.6/0.5 um (Dolphin Integration) |
Discovery AMS (Synopsys, Inc.) |
DMS Administrator (Mentor Graphics Corp.) |
DMS Component Engineer (Mentor Graphics Corp.) |
DMS Designer (Mentor Graphics Corp.) |
DMS Librarian (Mentor Graphics Corp.) |
DMS Procurement (Mentor Graphics Corp.) |
DMS Project Manager (Mentor Graphics Corp.) |
DMS Software Reengineering Toolkit (Semantic Designs, Inc.) |
DMS Web (Mentor Graphics Corp.) |
DMS-Xchange (Mentor Graphics Corp.) |
DMS-Xchange PartMiner CAPS DMS (Mentor Graphics Corp.) |
dROMet - 0.35 um (Dolphin Integration) |
dROMet ROM - 0.35 um (Dolphin Integration) |
Dual-Port RAM - 0.13 um (Dolphin Integration) |
Dual-Port RAM - 0.18 um (Dolphin Integration) |
Dual-Port RAM - 0.25 um (Dolphin Integration) |
Dual-Port RAM - 0.35 um (Dolphin Integration) |
Dual-Port RAM - 0.6/0.5 um (Dolphin Integration) |
DW 2000 (Design Workshop Technologies) |
DxDesigner (Mentor Graphics Corp.) |
DXL 1500 Bidrectional Verilog/EDIF netlist translator (Engineering DataXpress, Inc.) |
E3LCable (Mentor Graphics Corp.) |
eAnalyzer - Static Analysis and Verification Methodology Compliance System (Verisity Design, Inc.) |
EASI Developer Suite (Beach Solutions, Inc.) |
EASI-Diff (Beach Solutions, Inc.) |
EASI-Gen Family (Beach Solutions, Inc.) |
EASI-Studio (Beach Solutions, Inc.) |
eCelerator - Testbench Acceleration (Verisity Design, Inc.) |
Eclipse Boundary Scan Test (Intellitech Corp.) |
EDIF NETLIST TO SCHEMATIC CONVERTER (SoftJin Technologies Pvt., Ltd.) |
Eldo (Mentor Graphics Corp.) |
Eldo RF (Mentor Graphics Corp.) |
EMI-Lator (Alliance Semiconductor Corp.) |
Encore (Synopsys, Inc.) |
Enterprise (Synopsys, Inc.) |
eRM - e Reuse Methodology (Verisity Design, Inc.) |
ESP (Synopsys, Inc.) |
eVC - e Verification Component (Verisity Design, Inc.) |
Expedition PCB (Mentor Graphics Corp.) |
Expeditor Co-Emulation (Aptix Corp.) |
EZApi - Custom Rule Builder (VeriEZ Solutions, Inc.) |
EZCheck - Static Linter (VeriEZ Solutions, Inc.) |
EZReport - Verification Knowledge Extractor (VeriEZ Solutions, Inc.) |
EZTranslate (VeriEZ Solutions, Inc.) |
EZVerify (VeriEZ Solutions, Inc.) |
Fast Access Controller (Intellitech Corp.) |
FastMATH/FastMIPS Evaluation Kit (Intrinsity, Inc.) |
Fiesta CACT System Architecture Capture Tool (Comit Systems, Inc.) |
Fiesta CMBT memory BIST Controller Tool (Comit Systems, Inc.) |
Fiesta CMMT Simulation Memory Modeler (Comit Systems, Inc.) |
Fiesta CRST Register Specification Tool (Comit Systems, Inc.) |
Fiesta CSGT Synthesis Script Generation Tool (Comit Systems, Inc.) |
Fiesta CSMT Finite State Machine Editor (Comit Systems, Inc.) |
Fiesta CVXT Open Verification Environment (Comit Systems, Inc.) |
Fiesta CWGT Waveform & Constraints Generation Tool (Comit Systems, Inc.) |
FinVA (Fintronic USA, Inc.) |
FinVFI (Fintronic USA, Inc.) |
FlexTest (Mentor Graphics Corp.) |
Floorplan Compiler (Synopsys, Inc.) |
Flowtracer/EDA (Runtime Design Automation) |
Flowtracer/NC (Runtime Design Automation) |
Focus (FishTail Design Automation, Inc.) |
Formality (Synopsys, Inc.) |
FPGA Advantage (Mentor Graphics Corp.) |
FPGA Architect (Elanix, Inc.) |
Frequency Agile (Aeroflex Microelectronic Systems) |
FS-Test Boundary Scan Test Generation Software (Flynn Systems Corp.) |
GBR_RIP (Artwork Conversion Software, Inc.) |
GBR2DXF (Artwork Conversion Software, Inc.) |
GBRPLOT (Artwork Conversion Software, Inc.) |
GBRVU (Artwork Conversion Software, Inc.) |
GBRVU/X (Artwork Conversion Software, Inc.) |
GDS Compiler (Dolphin Integration) |
Genetic Algorithm and Direct Search Toolbox (The MathWorks, Inc.) |
GERBER UNION (Artwork Conversion Software, Inc.) |
Hardware/Software Co-Verification (Mentor Graphics Corp.) |
HDL Author (Mentor Graphics Corp.) |
HDL Designer Series (Mentor Graphics Corp.) |
HDL Detective (Mentor Graphics Corp.) |
HENRY (OEA International, Inc.) |
Hercules (Synopsys, Inc.) |
HiTas (AVERTEC) |
HSPICE (Synopsys, Inc.) |
HyperLynx EXT (Mentor Graphics Corp.) |
HyperLynx GHz (Mentor Graphics Corp.) |
IC Station SDL (Mentor Graphics Corp.) |
ICX/Tau (Mentor Graphics Corp.) |
Image Acquisition Toolbox (The MathWorks, Inc.) |
Incisive AMS (Cadence Design Systems, Inc.) |
InCyte (Chip Estimate Corp.) |
In-Target System Analyzer for Nios Embedded Processor (First Silicon Solutions, Inc. (FS2)) |
IP Creator, OCP/VCI Bridge Generator (Prosilog SA) |
IP Explorer (Synopsys, Inc.) |
IREM (Credence Systems Corp.) |
ISA-ACTEL51 (First Silicon Solutions, Inc. (FS2)) |
ISA-CAST51 In-Target System Analyzer (First Silicon Solutions, Inc. (FS2)) |
ISA-DSP24XX In-Target System Analyzer (First Silicon Solutions, Inc. (FS2)) |
ISA-eZ80 In-Target System Analyzer (First Silicon Solutions, Inc. (FS2)) |
ISA-GEODE System Analyzer (First Silicon Solutions, Inc. (FS2)) |
ISA-M8051EW In-Target System Analyzer (First Silicon Solutions, Inc. (FS2)) |
ISA-MIPS In-Target System Analyzer (First Silicon Solutions, Inc. (FS2)) |
ISA-QMIPS System Analyzer (First Silicon Solutions, Inc. (FS2)) |
ISA-ZSP500 In-Target System Analyzer (First Silicon Solutions, Inc. (FS2)) |
i-Virtual Stepper (Synopsys, Inc.) |
Kalos (Credence Systems Corp.) |
LAVIS (TOOL Corp.) |
LBISTArchitect (Mentor Graphics Corp.) |
LEDA Programmable Checker (Synopsys, Inc.) |
LeonardoSpectrum (Mentor Graphics Corp.) |
Libra-Passport (Synopsys, Inc.) |
Libra-Passport Library (Synopsys, Inc.) |
Library Analyzer (Z Circuit Automation, Inc.) |
Library Compiler (Synopsys, Inc.) |
Libra-Visa 0.18-micron Chartered library (Synopsys, Inc.) |
Link for ModelSim (The MathWorks, Inc.) |
Logical Cable (Mentor Graphics Corp.) |
Lyric AMS (Pulsic, Ltd.) |
Lyric Digital (Pulsic, Ltd.) |
Lyric ECO (Pulsic, Ltd.) |
Lyric Editor (Pulsic, Ltd.) |
Lyric Memory (Pulsic, Ltd.) |
Mach PA (Mentor Graphics Corp.) |
Mach TA (Mentor Graphics Corp.) |
Madam Univers Multi-core Software Debugger (AdvEDA BV) |
Magellan (Synopsys, Inc.) |
MaskCompose (Cadence Design Systems, Inc.) |
Maxwell 2D (Ansoft Corp.) |
Maxwell 3D (Ansoft Corp.) |
MBISTArchitect (Mentor Graphics Corp.) |
MemMax (Sonics, Inc.) |
MetaDeveloper Integrated Development Environment (ARC International) |
METAL (OEA International, Inc.) |
MetaSim (ARC International) |
MetaWare C/C++ Compiler (ARC International) |
METeor (VaST Systems Technology Corp.) |
Microtec C and C++ Compilers (Mentor Graphics Corp.) |
Milkyway (Synopsys, Inc.) |
Miss Univers HW/SW co-verification (AdvEDA BV) |
M-Link Option (Elanix, Inc.) |
MMAV (Denali Software, Inc.) |
Module Compiler (Synopsys, Inc.) |
MQX Real-Time Operating System (ARC International) |
Mrs Univers Stand-alone RTL simulator (AdvEDA BV) |
MSIM (Legend Design Technology, Inc.) |
Multimedia (ARC International) |
MyAnalog Station (MyCAD, Inc.) |
MyChip Station Pro (MyCAD, Inc.) |
MyLogic Station (MyCAD, Inc.) |
MyVHDL Station (MyCAD, Inc.) |
NanoSim (Synopsys, Inc.) |
NC-SystemC (Cadence Design Systems, Inc.) |
NC-Verilog (Cadence Design Systems, Inc.) |
NC-VHDL (Cadence Design Systems, Inc.) |
NEBULA Silicon Debugger (Intellitech Corp.) |
NeoCell Analog Physical Synthesis (Cadence Design Systems, Inc.) |
NET-AN (OEA International, Inc.) |
Network Processors (Agere Systems, Inc.) |
Nexxim (Ansoft Corp.) |
Octet (Credence Systems Corp.) |
OptEM Cable Designer (OptEM Engineering, Inc.) |
OptEM Connector (OptEM Engineering, Inc.) |
OptEm Inspector (OptEM Engineering, Inc.) |
OptEM Interconnect Designer (OptEM Engineering, Inc.) |
OptEM Package (OptEM Engineering, Inc.) |
Optimization Cockpit (Manhattan Routing, Inc. (MRI)) |
PacifIC Static Noise Analyzer (Cadence Design Systems, Inc.) |
Palladium (Cadence Design Systems, Inc.) |
Pathfinder IP Validation Station (Aptix Corp.) |
PCB Browser (Mentor Graphics Corp.) |
PCE RTL Power Estimation (BullDAST S.R.L.) |
PCI-Xactor Test Environment (Avery Design Systems, Inc.) |
Personal Kalos 2 (Credence Systems Corp.) |
PExprt (Ansoft Corp.) |
P-GRID (OEA International, Inc.) |
Physical Window (Manhattan Routing, Inc. (MRI)) |
Physically Knowledgeable Synthesis (Cadence Design Systems, Inc.) |
PICO Express (Synfora, Inc.) |
Pinnauq (SoftJin Technologies Pvt., Ltd.) |
Platform Express (Mentor Graphics Corp.) |
P-PLAN (OEA International, Inc.) |
Precision RTL Synthesis (Mentor Graphics Corp.) |
Prelude ECO (Pulsic, Ltd.) |
Prelude Physical Design Framework (Pulsic, Ltd.) |
PrimeTime SI (Synopsys, Inc.) |
PrimeTime: Static Timing Analysis (Synopsys, Inc.) |
PrimeXsys Platforms (ARM) |
PROCWizard (GiDEL, Ltd.) |
ProGenesis (Prolific, Inc.) |
Proteus, Progen, Prospector Full-Chip Optical Proximity Correction (Synopsys, Inc.) |
ProTiming (Prolific, Inc.) |
Prover CL (Prover Technology, Inc.) |
Prover dSpec (Prover Technology, Inc.) |
Prover eCheck (Prover Technology, Inc.) |
Prover eCheck Custom Logic Module (CLM) (Prover Technology, Inc.) |
Prover iLock (Prover Technology, Inc.) |
Prover SL (Prover Technology, Inc.) |
PSpice Studio (Cadence Design Systems, Inc.) |
PureSpec (Denali Software, Inc.) |
Q3D Extractor (Ansoft Corp.) |
QNX Momentics Development Suite Professional Edition (QNX Software Systems, Ltd.) |
Qt (Trolltech, Inc.) |
Qt Script for Applications (QSA) (Trolltech, Inc.) |
Qt Solutions (Trolltech, Inc.) |
Quartet One (Credence Systems Corp.) |
QuickSim II (Mentor Graphics Corp.) |
QuickView (Cadence Design Systems, Inc.) |
Quiet Expert (Mentor Graphics Corp.) |
RailMill (Synopsys, Inc.) |
Real Time DSP Architect (Elanix, Inc.) |
Regtify Register Management for Integrated Systems (Recardis) |
Resilient Packet Ring Controllers (Alliance Semiconductor Corp.) |
RF-PASS (OEA International, Inc.) |
RINCON Harmonic Balance simulator (AC Microwave GmbH) |
RING Designer (OEA International, Inc.) |
RMxprt (Ansoft Corp.) |
Scan Executive (Intellitech Corp.) |
Scan Executive (Intellitech Corp.) |
Scan Ring Linker (Intellitech Corp.) |
SeeCode Debugger (ARC International) |
shiftUp: Methodology Manager (InterWeave Tech Corp.) |
SignalStorm NDC (Cadence Design Systems, Inc.) |
Silicon Ensemble Physically Knowledgeable Synthesis (Cadence Design Systems, Inc.) |
Silicon Shuttle (UMC (United Microelectronics Corp.)) |
SiliconBackplane III (Sonics, Inc.) |
SimCluster (Avery Design Systems, Inc.) |
SimMechanics (The MathWorks, Inc.) |
SIMPLORER (Ansoft Corp.) |
Single-Port RAM - 0.13 um (Dolphin Integration) |
SiVL-LRC - Silicon vs. Layout Verification System (Synopsys, Inc.) |
SMASH (Dolphin Integration) |
SNAP (SynAPPS Software Corp.) |
SoC Encounter (Cadence Design Systems, Inc.) |
SoC Plan (Icinergy Software Company) |
SoC Preview (Icinergy Software Company) |
SoC Prototype (Icinergy Software Company) |
SoC Validation Lab (Aptix Corp.) |
Sonics3220 (Sonics, Inc.) |
SonicsStudio (Sonics, Inc.) |
Specman Elite - Testbench Automation (Verisity Design, Inc.) |
SPICE Explorer (Sandwork Design, Inc.) |
Spiral (OEA International, Inc.) |
Star-MTB (Synopsys, Inc.) |
Star-RCXT (Synopsys, Inc.) |
Star-SimXT (Synopsys, Inc.) |
Storage Disk Drive Electronics (Agere Systems, Inc.) |
SureCov - Automatic FSM, Expression, and Code Coverage (Verisity Design, Inc.) |
sVM - System Verification Methodology (Verisity Design, Inc.) |
SX-Link (Sandwork Design, Inc.) |
Sync (Alliance Semiconductor Corp.) |
System Studio (Synopsys, Inc.) |
System Verification (Mentor Graphics Corp.) |
SystemBIST (Intellitech Corp.) |
System-on-Chip Graphic Display Streamer (Dolphin Integration) |
Systemview (Elanix, Inc.) |
Taurus-WorkBench (Synopsys, Inc.) |
TeamPCB (Mentor Graphics Corp.) |
Telematics Hands-Free Systems (Agere Systems, Inc.) |
Testbencher Pro (SynaptiCAD, Inc.) |
TestDeveloper (Credence Systems Corp.) |
TestWizard (Avery Design Systems, Inc.) |
TranSACT (Mentor Graphics Corp.) |
TransBridge (Mentor Graphics Corp.) |
TransCable (Mentor Graphics Corp.) |
TransDesign (Mentor Graphics Corp.) |
TransLayout (Mentor Graphics Corp.) |
TransOVM (Mentor Graphics Corp.) |
TrustZone Technology (ARM) |
Turbo Package Analyzer (Ansoft Corp.) |
Turbo-MSIM High-Speed and High-Capacity Circuit Simulator (Legend Design Technology, Inc.) |
VBIT (Alternative System Concepts, Inc.) |
Vemo (Quintics, Inc.) |
Vera (Synopsys, Inc.) |
Verilog Front End (SoftJin Technologies Pvt., Ltd.) |
Verilog Test Suites (Verific Design Automation, Inc.) |
Verilogger Pro (SynaptiCAD, Inc.) |
Verity (Credence Systems Corp.) |
ViaPath (ViASIC, Inc.) |
Virtual Stepper (Synopsys, Inc.) |
Virtuoso AMS Designer Simulator (Cadence Design Systems, Inc.) |
Virtuoso AMS Silicon Analysis (Cadence Design Systems, Inc.) |
Virtuoso AMS-HF Silicon Analysis (Cadence Design Systems, Inc.) |
Virtuoso Analog Design Environment (Cadence Design Systems, Inc.) |
Virtuoso Analog ElectronStorm Option (Cadence Design Systems, Inc.) |
Virtuoso Analog VoltageStorm Option (Cadence Design Systems, Inc.) |
Virtuoso Aptivia Characterization and Modeling (Cadence Design Systems, Inc.) |
Virtuoso Aptivia Specification-driven Environment (Cadence Design Systems, Inc.) |
Virtuoso Chip Assembly Router (Cadence Design Systems, Inc.) |
Virtuoso Chip Editor (Cadence Design Systems, Inc.) |
Virtuoso Device Modeling (Cadence Design Systems, Inc.) |
Virtuoso Layout Editor (Cadence Design Systems, Inc.) |
Virtuoso Layout Migrate (Cadence Design Systems, Inc.) |
Virtuoso Multi-mode Simulation (Cadence Design Systems, Inc.) |
Virtuoso Schematic Editor (Cadence Design Systems, Inc.) |
Virtuoso Spectre Circuit Simulator (Cadence Design Systems, Inc.) |
Virtuoso Spectre RF Simulation Option (Cadence Design Systems, Inc.) |
Virtuoso UltraSim Full-chip Simulator (Cadence Design Systems, Inc.) |
Virtuoso XL Layout Editor (Cadence Design Systems, Inc.) |
vManager - Verification Management Solution (Verisity Design, Inc.) |
VoltageStorm (Cadence Design Systems, Inc.) |